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? 2010 freescale semiconductor, inc. all rights reserved. freescale semiconductor technical data due to feature similarities, this document covers both the mpc8568e and MPC8567E features. for simplicity, mpc8568 may only be mentioned throughout the document. the MPC8567E feature differences are as follows: ? the MPC8567E pci-express supports x1/x2/x4, but does not have x8 support. ? does not have etsec1, etsec2, or tlu note that both the mpc8568e and MPC8567E have their own pin assignment tables. contents 1. mpc8568e overview . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 10 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 4. input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . . . . . . 18 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. ethernet interface and mii management . . . . . . . . . . 26 9. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13. high-speed serial interfaces (hssi) . . . . . . . . . . . . . 61 14. pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 15. serial rapidio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 17. pic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 19. tdm/si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20. utopia/pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 21. hdlc, bisync, transparent and synchronous uart . . . . . . . . . . . . . . . . . . . . . . . . . . 96 22. package and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 99 23. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 24. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 25. system design information . . . . . . . . . . . . . . . . . . . 130 26. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 136 27. document revision history . . . . . . . . . . . . . . . . . . 138 mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications document number: mpc8568eec rev. 1, 10/2010
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 2 freescale semiconductor mpc8568e overview 1 mpc8568e overview this section provides a high-level overview of mpc8568e features. figure 1 shows the major functional units within the mpc8568e. figure 1. mpc8568e block diagram core complex x4/x2/x1 pci express 4x/1x rapidio and/or 66 mhz pci 32-bit 10/100/1gb mii, gmii, tbi, rtbi, rgmii, serial irqs sdram ddr flash sdram bus i 2 c i 2 c controller etsec 32-bit pci bus interface e500 coherency module ddr/ddr2/ memory controller local bus controller programmable interrupt controller (pic) duart e500 core 512-kbyte l2 cache/ sram 32-kbyte l1 instruction cache 32-kbyte l1 data cache ocean switch fabric serial rapidio and/or pci express 4-channel dma controller rmii mpc8568 security engine xor engine i 2 c i 2 c controller table lookup unit baud rate generators multi-user ram ucc8 parallel i/o accelerators dual 32-bit risc cp serial dma & 2 virtual dmas serial interface quicc engine? ucc7 ucc6 ucc5 ucc4 ucc3 ucc2 ucc1 mcc spi2 time slot assigner spi1 3 gmii/ 2 rgmii/tbi/rtbi 8 mii/ rmii 8 tdm ports 2 ul2/pos 10/100/1gb mii, gmii, tbi, rtbi, rgmii, etsec rmii zbt ram or x8 pci express
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 3 mpc8568e overview 1.1 mpcp8568e key features ? high-performance, power architecture? e500v2 core with 36-bit physical addressing ? 512 kbytes of level-2 cache ? quicc engine (qe) ? integrated security engine with xor acceleration ? two integrated 10/100/1gb enhanced three-speed ethernet controllers (etsecs) with tcp/ip acceleration and classification capabilities ? ddr/ddr2 memory controller ? table lookup unit (tlu) to access applicati on-defined routing topology and control tables ? 32-bit pci controller ? a 1x/4x serial rapidio? and/or x1/x2/x4 pci express interface. if x8 pci express is needed, then rapidio is not available due to the limitation of the pin multiplexing. ? programmable interrupt controller (pic) ? four-channel dma controller, two i 2 c controllers, duart, and local bus controller (lbc) note the mpc8568e and MPC8567E are also available without a security engine in a configuration known as the mpc8568 and mpc8567. all specifications other than those relating to security apply to the mpc8568 and mpc8567 exactly as described in this document. 1.2 mpc8568e architecture overview 1.2.1 e500 core and memory unit the mpc8568e contains a high-performance, 32-bit, book e?enhanced e500v2 power architecture core. in addition to 36-bit physical addressing, this version of the e500 core includes the following: ? double-precision floating-point apu?provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit gprs ? embedded vector and scalar single-precision floa ting-point apus?provide an instruction set for single-precision (32-bit) floating-point instructions the mpc8568e also contains 512 kbytes of l2 cache/sram, as follows: ? eight-way set-associative cache organization with 32-byte cache lines ? flexible configuration (can be configured as part cache, part sram) ? external masters can force data to be allocate d into the cache through programmed memory ranges or special transaction types (stashing). ? sram features include the following: ? i/o devices access sram regions by marking transactions as snoopable (global). ? regions can reside at any ali gned location in the memory map.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 4 freescale semiconductor mpc8568e overview ? byte-accessible ecc uses read-modify-write transaction accesses for smaller-than-cache-line accesses. 1.2.2 e500 coherency module (ecm) and address map the e500 coherency module (ecm) provides a mechanis m for i/o-initiated transactions to snoop the bus between the e500 core and the integrated l2 cache in order to maintain coherency across local cacheable memory. it also provides a flexible switch-type structure for core- and i/o-initiated transactions to be routed or dispatched to target modules on the device. the mpc8568e supports a flexible 36-bit physical address map. conceptually, the address map consists of local space and external address space. the local ad dress map is supported by eight local access windows that define mapping within the local 36-bit (64-gbyte) address space. the mpc8568e can be made part of a larger system address space through the mapping of translation windows. this functionality is included in the address translation and mapping units (atmus). both inbound and outbound translation windows are provided. the atmus allows the mpc8568e to be part of larger address maps such as the pci or pci express 64-bit address environment and the rapidio environment. 1.2.3 quicc engine ? integrated 8-port l2 ethernet switch ? 8 connection ports of 10/100 mbps mii/rmii & one cpu internal port ? each port supports four priority levels ? priority levels used with vlan tags or ip tos field to implement qos ? qos types of traffic, such as voice, video, and data ? includes support for the following protocols: ? atm sar up to 622 mbps (oc-12) full duplex, with atm traffic shaping (atf tm4.1) for up to 64k atm connections ? atm aal1 structured and unstructured circuit emulation service (ces 2.0) ? ima and atm transmission convergence sub-layer ? atm oam handling features compatible with itu-t i.610 ? ppp, multi-link (ml-ppp), multi-class (mc-ppp) and ppp mux in accordance with the following rfcs: 1661, 1662, 1990, 2686 and 3153 ? ip termination support for ipv4 and ipv6 packets including tos, ttl and header checksum processing ? atm (aal2/aal5) to ethernet (ip) interworking ? extensive support for atm statistics and ethernet rmon/mib statistics. ? 256 channels of hdlc/transparent or 128 channels of ss#7 ? includes support for the following serial interfaces: ? two ul2/pos-phy interfaces with 124 multi-phy addresses on utopia interface each or 31 multi-phy addresses on the pos interface each.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 5 mpc8568e overview ? three 1-gbps ethernet interfaces using three gmii, two rgmii/tbi/rtbi ? up to eight 10/100-mbps ethernet interfaces using mii or rmii ? up to eight t1/e1/j1/e3 or ds-3 serial interfaces 1.2.4 integrated security engine (sec) the sec is a modular and scalable security core optimized to process all the algorithms associated with ipsec, ike, wtls/wap, ssl/tls, and 3gpp. although it is not a protocol processor, the sec is designed to perform multi-algorithmic operations (for example, 3des-hmac-sha-1) in a single pass of the data. the version of the sec used in the mpc8568e is specifically capable of performing single-pass security cryptographic processing for ssl 3.0, ssl 3.1/tls 1.0, ipsec, srtp, and 802.11i. ? optimized to process all the algorithms associated with ipsec, ike, wtls/wap, ssl/tls, and 3gpp ? compatible with code written for the freescale mpc8541e and mpc8555e devices ? xor engine for parity checking in raid storage applications. ? four crypto-channels, each supporting multi-command descriptor chains ? cryptographic execution units: ? pkeu?public key execution unit ? deu?data encryption standard execution unit ? aesu?advanced encryption standard unit ? afeu?arc four execution unit ? mdeu?message digest execution unit ? keu?kasumi execution unit ? rng?random number generator 1.2.5 enhanced three-speed ethernet controllers the mpc8568e has two on-chip enhanced three-speed ethernet controllers (etsecs). the etsecs incorporate a media access control (mac) sublayer that supports 10- and 100-mbps and 1-gbps ethernet/802.3 networks with mii, rmii, gmii, rgmii, tbi, and rtbi physical interfaces. the etsecs include 2-kbyte receive and 10-kbyt e transmit fifos and dma functions. the mpc8568e etsecs support programmable crc ge neration and checking, rmon statistics, and jumbo frames of up to 9.6 kbytes. frame headers and buffer descriptors can be forced into the l2 cache to speed classification or other frame processing. they are ieee std 802.3?, ieee 802.3u, ieee 802.3x, ieee 802.3z, ieee 802.3ac, ieee 802.3ab-compatible. the buffer descriptors are based on the mpc8260 and mpc860t 10/100 ethernet programming models. each etsec can emulate a powerquicc iii tsec, allowing existing driver software to be re-used with minimal change. some of the key features of these controllers include: ? flexible configuration for multiple phy interface configurations. table 1 lists available configurations.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 6 freescale semiconductor mpc8568e overview ? tcp/ip acceleration and qos features: ? ip v4 and ip v6 header recognition on receive ? ip v4 header checksum verification and generation ? tcp and udp checksum verification and generation ? per-packet configurable acceleration ? recognition of vlan, stacked (queue in queue) vlan, 802.2, pppoe session, mpls stacks, and esp/ah ip-security headers ? supported in all fifo modes ? transmission from up to eight physical queues ? reception to up to eight physical queues ? full- and half-duplex ethernet support (1000 mbps supports only full duplex): ? ieee 802.3 full-duplex flow control (a utomatic pause frame generation or software-programmed pause frame generation and recognition) ? ieee std 802.1? virtual local area network (vlan) tags and priority ? vlan insertion and deletion ? per-frame vlan control word or default vlan for each etsec ? extracted vlan control word passed to software separately ? programmable ethernet preamble insertion and extraction of up to 7 bytes ? mac address recognition ? ability to force allocation of header information and buffer descriptors into l2 cache 1.2.6 ddr sdram controller the mpc8568e supports ddr sdram and ddr2 sdram. the memory interface controls main memory accesses and provides for a maximum of 16 gbytes of main memory. the mpc8568e supports a variety of sdram configurations. sdram banks can be built using dimms or directly-attached memory devices. sixteen multiple xed address signals provide for device densities of 64 mbits, 128 mbits, 256 mbits, 512 mbits, 1 gbits, 2 gbits and 4 gbits. four chip select signals support table 1. supported etsec1 and etsec2 configurations 1 1 both interfaces must use the same voltage (2.5 or 3.3 v). mode option etsec1 etsec2 ethernet standard interfaces tbi, gmii, or mii tbi, gmii, or mii ethernet reduced interfaces rtbi, rgmii, or rmii rtbi, rgmii, or rmii fifo and mixed interfaces 8-bit fifo tbi, gmii, mii, rtbi, rgmii, rmii, or 8-bit fifo tbi, gmii, mii, rtbi, rgmii, rmii, or 8-bit fifo 8-bit fifo 16-bit fifo not used/not available
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 7 mpc8568e overview up to four banks of memory. the mpc8568e supports bank sizes from 64 mbytes to 4 gbytes. nine column address strobes (mdm[0:8]) are used to provide byte selection for memory bank writes. the mpc8568e can be configured to retain the currently active sdram page for pipelined burst accesses. page mode support of up to 16 simultaneously open pages (32 for ddr2) can dramatically reduce access latencies for page hits. depending on the memory system design a nd timing parameters, using page mode can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page. using ecc, the mpc8568e detects and corrects all si ngle-bit errors and detect s all double-bit errors and all errors within a nibble. the mpc8568e can invoke a level of system power management by asserting the mcke sdram signal on-the-fly to put the memory into a low-power sleep mode. 1.2.7 table lookup unit (tlu) the table lookup unit (tlu) provides access to applicati on-defined routing topology and control tables in external memory. it accesses an external memory array attached to the local bus controller (lbc). communication between the cpu and the tlu occurs via messages passed through the tlu?s memory-mapped configuration and status registers. the tlu provides resources for efficient generation of table entry addresses in memory, hash generation of addresses, and binary table searching algorit hms for both exact-match and longest-prefix-match strategies.it supports the following tlu complex table types: ? hash-trie-key table for hash-based exact-match algorithms ? chained-hash table for partially inde xed and hashed exact-match algorithms ? longest-prefix-match algorithm ? flat-data table for retrieving search results and simple indexed algorithms 1.2.8 pci controller the mpc8568e supports one 32-bit pci controller, which supports speeds of up to 66 mhz. other features include: ? compatible with the pci local bus specification, revision 2.2, supporting 32- and 64-bit addressing ? can function as host or agent bridge interface ? as a master, supports read and write operations to pci memory space, pci i/o space, and pci configuration space ? can generate pci special-cycle and interrupt-acknowledge commands. as a target, it supports read and write operations to system memory as well as configuration accesses. ? supports pci-to-memory and memory-to-pci streaming, memory prefetching of pci read accesses, and posting of processor-to-pci and pci-to-memory writes ? pci 3.3-v compatible with select able hardware-enforced coherency
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 8 freescale semiconductor mpc8568e overview 1.2.9 high speed i/o interfaces the mpc8568e supports two high-speed i/o interface standards: serial rapidio and pci express. it can be configured as x1/x4 srio and 1x/2x/4x pci express simultaneously with the following limitation: ? both srio and pci-express are limited to use the same clock and are limited to 2.5g. ? spread spectrum clocking can not be used because srio doesn't support this (pci-express does support it). if x8 pci express is needed, then srio is not available due to the pin multiplex limitation. 1.2.10 serial rapidio the serial rapidio interface is based on the rapidio interconnect specification, revision 1.2 . rapidio is a high-performance, point-to-point, low-pin-count, pack et-switched system-level interconnect that can be used in a variety of applications as an open sta ndard. the rapidio architecture has a rich variety of features including high data bandwidth, low-latenc y capability, and support for high-performance i/o devices, as well as support for message-passing and software-managed programming models. key features of the serial rapidio interface unit include: ? support for rapidio interconnect specification, revision 1.2 (all transaction flows and priorities) ? both 1x and 4x lp-serial link interfaces, with tr ansmission rates of 1.25, 2.5, and 3.125 gbaud (data rates of 1.0, 2.0, and 2.5 gbps) per lane ? auto detection of 1x or 4x mode operation during port initialization ? 34-bit addressing and up to 256-byte data payload ? receiver-controlled flow control ? support for rapidio error injection the rapidio messaging unit supports two inbox/out box mailboxes (queues) fo r data and one doorbell message structure. both chaining and direct modes are provided for the outbox, and messages can hold up to 16 packets of 256 bytes, or a total of 4 kbytes. 1.2.11 pci express interface the mpc8568e supports a pci express interface compatible with the pci express base specification revision 1.0a . it is configurable at boot time to act as e ither root complex or e ndpoint.the physical layer of the pci express interface operates at a 2.5-gbaud data rate per lane. other features of the pci express interface include: ? x8, x4, x2, and x1 link widths supported ? selectable operation as root complex or endpoint ? both 32- and 64-bit addressing and 256-byte maximum payload size ? full 64-bit decode with 32-bit wide windows
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 9 mpc8568e overview 1.2.12 programmable interrupt controller (pic) the mpc8568e pic implements the logic and programming structures of the openpic architecture, providing for external interrupts (with fully nested in terrupt delivery), message interrupts, internal-logic driven interrupts, and global high-resolution timers. up to 16 programmable interrupt priority levels are supported. the pic can be bypassed to allow use of an external interrupt controller. 1.2.13 dma controller, i 2 c, duart, and local bus controller the mpc8568e provides an integrated four-channel dma controller, which can tran sfer data between any of its i/o or memory ports or between two devices or locations on the same port. the dma controller also: ? allows chaining (both extended and direct) through local memory-mapped chain descriptors. ? scattering, gathering, and misaligned transfers ar e supported. in addition, stride transfers and complex transaction chaining are supported. ? local attributes such as snoop and l2 write stashing can be specified. there are two i 2 c controllers. these synchronous, multimaster buses can be connected to additional devices for expansion and system development. the duart supports full-duplex operation and is compatible with the pc16450 and pc16550 programming models. 16-byte fifos are supporte d for both the transmitter and the receiver. the mpc8568e local bus controller (lbc) port allows connections with a wide variety of external memories, dsps, and asics. three separate state machines share the same external pins and can be programmed separately to access different types of devices. the general-purpose chip select machine (gpcm) controls accesses to asynchronous devices using a simple handshake protocol. the user programmable machine (upm) can be programmed to interface to synchronous devices or custom asic interfaces. the sdram controller provides access to standard sdram. each chip select can be configured so that the associated chip interface can be controlled by the gpcm, upm, or sdram controller. all may exist in the same system. the local bus controller supports the following features: ? multiplexed 32-bit address and data bus operating at up to 133 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller ? three protocol engines availa ble on a per-chip-select basis ? parity support ? default boot rom chip select with configurable bus width (8, 16, or 32 bits) ? supports zero-bus-turnaround (zbt) ram 1.2.14 power management in addition to low-voltage opera tion and dynamic power management, which au tomatically minimizes power consumption of blocks when they are idle, four power consumption modes are supported: full on, doze, nap, and sleep.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 10 freescale semiconductor electrical characteristics 1.2.15 system performance monitor the performance monitor facility supports eight 32-bit counters that can count up to 512 counter-specific events. it supports duration and quantity threshold c ounting and a burstiness feature that permits counting of burst events with a programmable time between bursts. 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8568e. this device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 2. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.21 v ? pll supply voltage av dd _ plat , av dd _ core, av dd _ ce, av dd _ pci, av dd _ lbiu, av dd _ srds ?0.3 to 1.21 v ? core power supply for serdes transceiver scorevdd ?0.3 to 1.21 v ? pad power supply for serdes transceiver xv dd ?0.3 to 1.21 v ? ddr and ddr2 dram i/o voltage gv dd ?0.3 to 2.75 ?0.3 to 1.98 v? etsec1, etsec2 i/o voltage lv dd ?0.3 to 3.63 ?0.3 to 2.75 v? qe ucc1/ucc2 ethernet interface i/o voltage tv dd ?0.3 to 3.63 ?0.3 to 2.75 v? pci, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v 3 local bus i/o voltage bv dd ?0.3 to 3.63 ?0.3 to 2.75 v3
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 11 electrical characteristics 2.1.2 recommended operating conditions table 3 provides the recommended operating conditions fo r this device. note that the values in table 3 are the recommended and tested operating conditions. proper device operation outside these conditions is not guaranteed. input voltage ddr/ddr2 dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 5 ddr/ddr2 dram reference mv ref ?0.3 to (gv dd + 0.3) v 2, 5 three-speed ethernet signals lv in tv in ?0.3 to (lv dd + 0.3) ?0.3 to (tv dd + 0.3) v4, 5 local bus signals bv in ?0.3 to (bv dd + 0.3) ? duart, sysclk, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 5 pci ov in ?0.3 to (ov dd + 0.3) v 6 storage temperature range t stg ?55 to 150 ?c c? notes: 1. functional and tested operating conditions are given in ta b l e 3 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: l/tv in must not exceed l/tv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . 6. ov in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 2 . table 3. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.1 v 55 mv v ? pll supply voltage av dd _ plat , av dd _ core, av dd _ ce, av dd _ pci, av dd _ lbiu, av dd _ srds 1.1 v 55 mv v ? core power supply for serdes transceiver scorevdd 1.1 v 55 mv v ? pad power supply for serdes transceiver xv dd 1.1 v 55 mv v ? ddr and ddr2 dram i/o voltage gv dd 2.5 v 125 mv 1.8 v 90 mv v? table 2. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 12 freescale semiconductor electrical characteristics figure 2 shows the undershoot and overshoot voltages at the interfaces of the mpc8568e. figure 2. overshoot/undershoot voltage for bv dd /gv dd /lv dd /tv dd /ov dd three-speed ethernet i/o voltage lv dd tv dd 3.3 v 165 mv 2.5 v 125 mv v? pci, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 165 mv v ? local bus i/o voltage bv dd 3.3 v 165 mv 2.5 v 125 mv v? input voltage ddr and ddr2 dram signals mv in gnd to gv dd v? ddr and ddr2 dram reference mv ref gnd to gv dd /2 v ? three-speed ethernet signals lv in tv in gnd to lv dd gnd to tv dd v? local bus signals bv in gnd to bv dd v? pci, duart, sysclk, system control and power management, i 2 c, and jtag signals ov in gnd to ov dd v? junction temperature range tj 0 to105 o c? table 3. recommended operating conditions (continued) characteristic symbol recommended value unit notes gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% b/g/l/t/ov dd + 20% b/g/l/t/ov dd b/g/l/t/ov dd + 5% of t clock 1 1. note that t clock refers to the clock period associated with the respective interface v ih v il note: for i2c and jtag, t clock references sysclk. for ddr, t clock references mclk. for etsec, tclock references ec_gtx_clk125. for lbiu, t clock references lclk. for pci, t clock references pci_clk or sysclk. for serdes, t clock references sd_ref_clk. 2. note that with the pci overshoot allowed (as specified above), the device does not fully comply with the maximum ac ratings and device protection guideline outlined in the pci rev. 2.2 standard (section 4.2.2.3)
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 13 electrical characteristics the core voltage must always be provided at nominal 1.1v. (see table 3 for actual recommended core voltage). voltage to the processor interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 3 . the input voltage threshold scales with respect to the associated i/o supply voltage. ov dd and lv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram interface uses a single-ended differential receiver referenced the externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the sstl2 electrical signaling standard. 2.1.3 output driver characteristics table 4 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.2 power sequencing the mpc8568e requires its power rails to be applied in specific sequence in order to ensure proper device operation. these requirements are as follows for power up: 1. v dd , av dd _ n , bv dd , scorev dd , lv dd , tv dd , xv dd , ov dd 2. gv dd all supplies must be at their stable values within 50 ms. table 4. output drive capability driver type programmable output impedance ( ) supply voltage notes local bus interface utilities signals 25 25 bv dd = 3.3 v bv dd = 2.5 v 1 45(default) 45(default) bv dd = 3.3 v bv dd = 2.5 v pci signals 25 ov dd = 3.3 v 2 42 (default) ddr signal 20 gv dd = 2.5 v ? ddr2 signal 16 32 (half strength mode) gv dd = 1.8 v ? etsec 10/100/1000 signals 42 l/tv dd = 2.5/3.3 v ? duart, system control, jtag 42 ov dd = 3.3 v ? i2c 150 ov dd = 3.3 v ? notes: 1 . the drive strength of the local bus interface is determined by the configuration of the appropriate bits in porimpscr. 2. the drive strength of the pci interface is determined by the setting of the pci_gnt[1] signal at reset.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 14 freescale semiconductor power characteristics note items on the same line have no orderi ng requirement with respect to one another. items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. in order to guarantee mcke low duri ng power-up, the above sequencing for gvdd is required. if there is no concern about any of the ddr signals being in an indeterminate state duri ng power-up, then the sequencing for gvdd is not required. 3 power characteristics the power dissipation of v dd for various core complex bus (ccb) versus the core and qe frequency for mpc8568e is shown in table 5 . note that this is based on the design estimate only. more accurate power number will be available after we ha ve done the measurement on the silicon. table 5. mpc8568e power dissipation ccb frequency core frequency qe frequency typical 65 c typical 105 c maximum unit 400 800 400 8.7 12.0 13.0 w 400 1000 400 8.9 12.3 13.6 w 400 1200 400 11.3 15.7 16.9 w 533 1333 533 12.4 17.2 18.7 w notes: 1. ccb frequency is the soc platform frequency which corresponds to ddr data rate. 2. typical 65 c based on v dd =1.1v, tj=65. 3. typical 105 c based on v dd =1.1v, tj=105. 4. maximum based on v dd =1.1v, tj=105. table 6. typical mpc8568e i/o power dissipation interface parameters gv dd bv dd ov dd lv dd tv dd xv dd unit comment 2.5 v 1.8 v 3.3 v 2.5 v 3.3 v 2.5 v 3.3 v 2.5 v ddr/ddr2 333 mhz 0.76 0.50 w data rate 64-bit with ecc 60% utilization 400 mhz 0.56 w 533 mhz 0.68 w local bus 33 mhz, 32b 0.07 0.04 w ? 66 mhz, 32b 0.13 0.07 w ? 133 mhz, 32b 0.24 0.14 w ? pci 33 mhz 0.04 w ? 66 mhz 0.07 w ? srio 4x, 3.125g 0.49 w ? pci express 8x, 2.5g 0.71 w ?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 15 input clocks 4 input clocks 4.1 system clock timing table 7 provides the system clock (sysclk) ac timing specifications for the mpc8568e. etsec ethernet mii 0.01 w multiply with number of the interfaces gmii/tbi 0.07 w rgmii/rtbi 0.04 w etsec fifo i/o 16b, 200 mhz 0.20 w multiply with number of the interfaces 16b, 155 mhz 0.16 w 8b, 200 mhz 0.11 w 8b, 155 mhz 0.08 w qe ucc mii/rmii 0.01 w multiply with number of the interfaces if ucc is programmed for other protocols, scale ethernet power dissipation to the number of signals and the clock rate gmii/tbi 0.07 w rgmii/rtbi 0.04 w note: this is the power for each individual interface. the power must be calculated for each interface being utilized. table 7. sysclk ac timing specifications at recommended operating conditions (see ta b l e 3 ) with ov dd = 3.3 v 165 mv . parameter/condition symbol min typical max unit notes sysclk frequency f sysclk ? ? 166 mhz 1 sysclk cycle time t sysclk 6.0 ? ? ns ? sysclk rise and fall time t kh , t kl 0.61.02.3ns 2 sysclk duty cycle t khk /t sysclk 40 ? 60 % 3 table 6. typical mpc8568e i/o power dissipation (continued) interface parameters gv dd bv dd ov dd lv dd tv dd xv dd unit comment 2.5 v 1.8 v 3.3 v 2.5 v 3.3 v 2.5 v 3.3 v 2.5 v
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 16 freescale semiconductor input clocks 4.2 pci clock timing table 8 provides the pci clock (pci_clk) ac timing specifications for the mpc8568e. 4.3 real time clock timing the rtc input is sampled by the platform clock (ccb clock). the output of the sampling latch is then used as an input to the counters of the pic and the time base unit of the e500. there is no need for jitter specification. the minimum pulse width of the rtc signal should be greater than 2x the period of the ccb clock. that is, minimum clock high time is 2 t ccb , and minimum clock low time is 2 t ccb . there is no minimum rtc frequency. rtc may be grounded if not needed. sysclk jitter ? ? ? +/? 150 ps 4, 5 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 core frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 23.2, ?ccb/sysclk pll ratio and section 23.3, ?e500 core pll ratio ,? for ratio settings. 2. rise and fall times for sysclk are measured at 0.4 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the sysclk driver?s closed loop jitter bandwidth should be <500 khz at -20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers with the specified jitter. table 8. pci_clk ac timing specifications at recommended operating conditions (see ta b l e 3 ) with ov dd = 3.3 v 165 mv . parameter/condition symbol min typical max unit notes pci_clk frequency f pci_clk ??66.7mhz? pci_clk cycle time t pci_clk 15 ? ? ns ? pci_clk rise and fall time t kh , t kl 0.6 1.0 2.3 ns 1 pci_clk duty cycle t khk /t pci_clk 40 ? 60 % 2 pci_clk jitter ? ? ? +/? 150 ps 3,4 notes: 1. rise and fall times for pci_clk are measured at 0.4 v and 2.7 v. 2. timing is guaranteed by design and characterization. 3. this represents the total input jitter?short term and long term?and is guaranteed by design. 4. the sysclk driver?s closed loop jitter bandwidth should be <500 khz at -20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers with the specified jitter. table 7. sysclk ac timing specifications (continued) at recommended operating conditions (see ta b l e 3 ) with ov dd = 3.3 v 165 mv . parameter/condition symbol min typical max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 17 input clocks 4.4 etsec gigabit reference clock timing table 9 provides the etsec gigabit reference clocks (ec_gtx_clk125) ac timing specifications for the mpc8568e. 4.5 fifo clock speed restrictions note the following fifo maximum speed restrictions based on the platform speed. for fifo gmii mode: fifo tx/rx clock frequency <= pl atform clock frequency / 4.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no higher than 127 mhz. for fifo encoded mode: fifo tx/rx clock frequency <= platform clock frequency / 3.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no higher than 167 mhz 4.6 other input clocks for information on the input clocks of other functional blocks of the platform such as serdes, and etsec, see the specific section of this document. table 9. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typical max unit notes ec_gtx_clk125 frequency f g125 ?125?mhz? ec_gtx_clk125 cycle time t g125 ?8?ns? ec_gtx_clk125 rise and fall time l/tvdd = 2.5 v l/tvdd = 3.3 v t g125r, t g125f ? ? ? ? 0.75 1.0 ns ? ec_gtx_clk125 duty cycle gmii, tbi 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %1, 2 notes: 1. timing is guaranteed by design and characterization. 2. ec_gtx_clk125 is used to generate the gtx clock for the etsec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosened from 47/53% as long as the phy device can tolerate the duty cycle generated by the etsec gtx_clk. see section 8.2.6, ?rgmii and rtbi ac timing specifications ,? for duty cycle for 10base-t and 100base-t reference clock. 3. rise and fall times for ec_gtx_clk125 are measured from 0.5 and 2.0 v for l/tvdd = 2.5 v, and from 0.6 and 2.7 v for l/tvdd = 3.3 v.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 18 freescale semiconductor reset initialization 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the mpc8568e. table 10 provides the reset initialization ac timing specifications for the ddr sdram component(s). table 11 provides the pll lock times. 6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8568e. note that ddr sdram is gv dd (typ) = 2.5 v and ddr2 sdram is gv dd (typ) = 1.8 v. table 10. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset 100 ? s? minimum assertion time for sreset 3 ? sysclks 1 pll input setup time with stable sysclk before hreset negation 100 ? s? input setup time for por configs (other than pll config) with respect to negation of hreset 4 ? sysclks 1 input hold time for all por configs (including pll config) with respect to negation of hreset 2 ? sysclks 1 maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks 1 notes: 1. sysclk is the primary clock input for the mpc8568e. table 11. pll lock times parameter/condition min max unit notes platform pll lock times ? 100 s? qe pll lock times ? 100 s? cpu pll lock times ? 100 s? pci pll lock times ? 100 s? local bus pll ? 100 s?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 19 ddr and ddr2 sdram 6.1 ddr sdram dc electrical characteristics table 12 provides the recommended operating conditions for the ddr2 sdram component(s) of the mpc8568e when gv dd (typ) = 1.8 v . table 13 provides the ddr capacitance when gv dd (typ) = 1.8 v. table 14 provides the recommended operating conditions for the ddr sdram component(s) when gv dd (typ) = 2.5 v . table 12. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.7 1.9 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ?0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref +0.125 gv dd +0.3 v ? input low voltage v il ?0.3 mv ref ? 0.125 v ? output leakage current i oz ?10 10 a4 output high current (v out = 1.420 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 13. ddr2 sdram capacitance for gv dd (typ)=1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 14. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.3 2.7 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.15 gv dd + 0.3 v ?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 20 freescale semiconductor ddr and ddr2 sdram table 15 provides the ddr capacitance when gv dd (typ)=2.5 v. table 16 provides the current draw characteristics for mv ref . input low voltage v il ?0.3 mv ref ? 0.15 v ? output leakage current i oz ?10 10 a4 output high current (v out = 1.95 v) i oh ?16.2 ? ma ? output low current (v out = 0.35 v) i ol 16.2 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 15. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a =25c, v out = gvdd/2, v out (peak-to-peak) = 0.2 v. table 16. current draw characteristics for mv ref parameter / condition symbol min max unit note current draw for mv ref i mvref ? 500 a1 1. the voltage regulator for mv ref must be able to supply up to 500 a current. table 14. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v (continued) parameter/condition symbol min max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 21 ddr and ddr2 sdram 6.2 ddr sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr sdram interface. 6.2.1 ddr sdram input ac timing specifications table 17 provides the input ac timing specifications for the ddr2 sdram when gv dd (typ)= 1.8 v. table 18 provides the input ac timing specifications for the ddr sdram when gv dd (typ)=2.5 v. table 19 provides the input ac timing specifications for the ddr sdram interface. table 17. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.25 v ? ac input high voltage v ih mv ref + 0.25 ? v ? table 18. ddr sdram input ac timing specifications for 2.5-v interface at recommended operating conditions. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ? ac input high voltage v ih mv ref + 0.31 ? v ? table 19. ddr sdram input ac timing specifications at recommended operating conditions. parameter symbol min max unit notes controller skew for mdqs?mdq/mecc/mdm t ciskew ps 1, 2 533 mhz ?300 300 3 400 mhz ?365 365 ? 333 mhz ?390 390 ? note: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equation: t diskew =+/-(t/4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . 3. maximum ddr1 frequency is 400 mhz.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 22 freescale semiconductor ddr and ddr2 sdram figure 3 provides the input timing diagram for the ddr sdram interface. t diskew can be calculated from t ciskew . see table 19 footnote 2. figure 3. ddr sdram input timing diagram 6.2.2 ddr sdram output ac timing specifications table 20. ddr sdram output ac timing specifications at recommended operating conditions. parameter symbol 1 min max unit notes mck[n] cycle time, mck[n]/mck [n] crossing t mck 3.75 10 ns 2 addr/cmd output setup with respect to mck t ddkhas ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? 333 mhz 2.40 ? addr/cmd output hold with respect to mck t ddkhax ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? 333 mhz 2.40 ? mcs [n] output setup with respect to mck t ddkhcs ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? 333 mhz 2.40 ? mdq[x] mdqs[n] mck [n] mck[n] t mck t diskew t diskew d1 d0
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 23 ddr and ddr2 sdram mcs [n] output hold with respect to mck t ddkhcx ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? 333 mhz 2.40 ? mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mdq/mecc/mdm output setup with respect to mdqs t ddkhds, t ddklds ps 5 533 mhz 538 ? 7 400 mhz 700 ? 333 mhz 900 ? mdq/mecc/mdm output hold with respect to mdqs t ddkhdx, t ddkldx ps 5 533 mhz 538 ? 7 400 mhz 700 ? 333 mhz 900 ? mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck +0.6 ns 6 mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8568e integrated communications processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[n] at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. 7. maximum ddr1 frequency is 400 mhz table 20. ddr sdram output ac timing specifications (continued) at recommended operating conditions. parameter symbol 1 min max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 24 freescale semiconductor ddr and ddr2 sdram note for the addr/cmd setup and hold specifications in table 20 , it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. figure 4 shows the ddr sdram output timing for the mck to mdqs skew measurement (tddkhmh). figure 4. timing diagram for tddkhmh mdqs mck [n] mck[n] t mck t ddkhmhmax) = 0.6 ns t ddkhmh(min) = ?0.6 ns mdqs
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 25 duart figure 5 shows the ddr sdram output timing diagram. figure 5. ddr sdram output timing diagram figure 6 provides the ac test load for the ddr bus. figure 6. ddr ac test load 7duart this section describes the dc and ac electri cal specifications for the duart interface of the mpc8568e. 7.1 duart dc electrical characteristics table 21 provides the dc electrical characteristics for the duart interface. table 21. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ? 0.3 0.8 v addr/cmd t ddkhas ,t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp output z 0 = 50 r l = 50 gv dd /2
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 26 freescale semiconductor ethernet interface and mii management 7.2 duart ac electrical specifications table 22 provides the ac timing parameters for the duart interface. 8 ethernet interface and mii management this section provides the ac and dc electrical char acteristics for etsec, mii management and ethernet interface inside quicc engine. note that etsec and qe ethernet have the same dc/ac characteristics. 8.1 gmii/mii/tbi/rgmii/rtbi/rmii electrical characteristics the electrical characteristics specified here apply to all gigabit media independent interface (gmii), media independent interface (mii), ten-bit interface (tbi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data i nput/output (mdio) and management data clock (mdc). the rgmii and rtbi interfaces are defined for 2.5 v, while the gmii and tbi interfaces can be operated at 3.3 or 2.5 v. whether the gmii, mii, or tbi interface is operated at 3.3 or 2.5 v, the timing is compatible with the ieee 802.3 standard. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 (12/10/2000). the rmii interface follows the rmii consortium rmii input current (v in 1 = 0 v or v in = v dd) i in ?10 a high-level output voltage (ov dd = min, i oh = ?100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in tab le 2 and ta ble 3 . table 22. duart ac timing specifications parameter value unit notes minimum baud rate ccb clock/1,048,576 baud 1,2 maximum baud rate ccb clock/16 baud 1,3 oversample rate 16 ? 1,4 notes: 1. guaranteed by design 2. ccb clock refers to the platform clock. 3. actual attainable baud rate will be limited by the latency of interrupt processing. 4. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample. table 21. duart dc electrical characteristics (continued) parameter symbol min max unit
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 27 ethernet interface and mii management specification version 1.2 (3/20/1998). the electrical ch aracteristics for mdio and mdc are specified in section 8, ?ethernet interface and mii management.? 8.1.1 ethernet interface dc electrical characteristics all gmii, mii, tbi, rgmii, rmii and rtbi drivers and receivers comply with the dc parametric attributes specified in table 23 and table 24 . the potential applied to the input of a gmii, mii, tbi, rgmii, rmii or rtbi receiver may exceed the potential of the receiver?s power supply (that is, a gmii driver powered from a 3.6-v supply driving v oh into a gmii receiver powered from a 2.5-v supply). tolerance for dissimilar gmii driver and receiver suppl y potentials is implicit in these specifications. the rgmii and rtbi signals are based on a 2.5-v cmos interface voltage as defined by jedec eia/jesd8-5. table 23. gmii, mii, rmii, and tbi dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3 v lv dd tv dd 3.135 3.465 v 1, 2 output high voltage (lv dd /tv dd = min, ioh = ?4.0 ma) voh 2.40 lv dd /tv dd + 0.3 v ? output low voltage (lv dd /tv dd = min, iol = 4.0 ma) vol gnd 0.50 v ? input high voltage v ih 2.0 lv dd /tv dd + 0.3 v ? input low voltage v il ?0.3 0.90 v ?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 28 freescale semiconductor ethernet interface and mii management 8.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for fifo, gmii, mii, tbi, rgmii, rmii and rtbi are presented in this section. 8.2.1 fifo ac specifications the basis for the ac specifications for the etsec?s fifo modes is the double data rate rgmii and rtbi specifications, since they have similar performance a nd are described in a source-synchronous fashion like fifo modes. however, the fifo interface provides de liberate skew between the transmitted data and source clock in gmii fashion. input high current (v in = lv dd , v in = tv dd ) i ih ?40 a 1, 2, 3 input low current (v in = gnd) i il ?600 ? a3 notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports qe ucc1 and ucc2 ethernet ports. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta ble 2 and ta ble 3 . table 24. gmii, mii, rmii, rgmii, rtbi, tbi and fifo dc electrical characteristics parameters symbol min max unit notes supply voltage 2.5 v lv dd /tv dd 2.37 2.63 v 1, 2 output high voltage (lv dd /tv dd = min, ioh = ?1.0 ma) v oh 2.00 lv dd /tv dd + 0.3 v ? output low voltage (lv dd /tv dd = min, i ol = 1.0 ma) v ol gnd ? 0.3 0.40 v ? input high voltage v ih 1.70 lv dd /tv dd + 0.3 v ? input low voltage v il ?0.3 0.70 v ? input high current (v in = lv dd , v in = tv dd ) i ih ?10 a1, 2, 3 input low current (v in = gnd) i il ?15 ? a3 note: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports qe ucc1 and ucc2 ethernet ports. 3. note that the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta b l e 2 and ta b l e 3 . table 23. gmii, mii, rmii, and tbi dc electrical characteristics (continued) parameter symbol min max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 29 ethernet interface and mii management when the etsec is configured for fifo modes, all clocks are supplied from external sources to the relevant etsec interface. that is, the transmit clock must be applied to the etsec n ?s tsec n _tx_clk, while the receive clock must be applied to pin tsec n _rx_clk. the etsec internally uses the transmit clock to synchronously generate tr ansmit data and outputs an echoed copy of the transmit clock back out onto the tsec n _gtx_clk pin (while transmit data appears on tsec n _txd[7:0], for example). it is intended that external receivers capture etsec transmit data using the clock on tsec n _gtx_clk as a source- synchronous timing reference. typically, the cloc k edge that launched the data can be used, since the clock is delayed by the etsec to allow acceptable set-up margin at the receiver. note that there is relationship between the maximum fifo speed and the platform speed. for more information see section 4.4, ?platform to fifo restrictions. a summary of the fifo ac specifications appears in table 25 and table 26 . table 25. fifo mode transmit ac timing specification parameter/condition symbol min typ max unit tx_clk, gtx_clk clock period t fit 5.0 8.0 100 ns tx_clk, gtx_clk duty cycle t fith 45 50 55 % tx_clk, gtx_clk peak-to-peak jitter t fitj ? ? 250 ps rise time tx_clk (20%?80%) t fitr ?0.751.5 ns fall time tx_clk (80%?20%) t fitf ?0.751.5 ns fifo data txd[7:0], tx_er, tx_en setup time to gtx_clk t fitdv 2.0 ? ? ns gtx_clk to fifo data txd[7:0], tx_er, tx_en hold time t fitdx 0.5 1 ?3.0ns table 26. fifo mode receive ac timing specification parameter/condition symbol min typ max unit rx_clk clock period t fir 5.0 8.0 100 ns rx_clk duty cycle t firh /t firh 45 50 55 % rx_clk peak-to-peak jitter t firj ??250ps rise time rx_clk (20%?80%) t firr ?0.751.5 ns fall time rx_clk (80%?20%) t firf ?0.751.5 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t firdv 1.5 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t firdx 0.5 ? ? ns
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 30 freescale semiconductor ethernet interface and mii management timing diagrams for fifo appear in figure 7 and figure 8 . . figure 7. fifo transmit ac timing diagram figure 8. fifo receive ac timing diagram 8.2.2 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 8.2.2.1 gmii transmit ac timing specifications table 27 provides the gmii transmit ac timing specifications. table 27. gmii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t gtx ?8.0? ns gtx_clk duty cycle t gtxh /t gtx 45 ? 55 % gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ? ? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk data clock rise time (20%-80%) t gtxr 2 ?1.02.0ns gtx_clk data clock fall time (80%-20%) t gtxf 2 ?1.02.0ns ec_gtx_clk125 clock rise time (20%-80%) t g125r ?1.02.0ns ec_gtx_clk125 clock fall time (80%-20%) t g125f ?1.02.0ns t fit t fith t fitf t fitdx txd[7:0] tx_en gtx_clk tx_er t fitdv t fitr t fir t firh t firf t firr rx_clk rxd[7:0] rx_dv rx_er valid data t firdx t firdv
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 31 ethernet interface and mii management figure 9 shows the gmii transmit ac timing diagram. figure 9. gmii transmit ac timing diagram 8.2.2.2 gmii receive ac timing specifications table 28 provides the gmii receive ac timing specifications. ec_gtx_clk125 duty cycle t g125h /t g125 45 55 ns notes: 1. the symbols used for timing specifications herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design table 28. gmii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period t grx ?8.0? ns rx_clk duty cycle t grxh /t grx 40 ? 60 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ? ? ns rx_clk clock rise (20%-80%) t grxr 2 ?1.02.0ns table 27. gmii transmit ac timing specifications (continued) at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 32 freescale semiconductor ethernet interface and mii management figure 10 provides the ac test load for etsec. figure 10. etsec ac test load figure 11 shows the gmii receive ac timing diagram. figure 11. gmii receive ac timing diagram 8.2.3 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. rx_clk clock fall time (80%-20%) t grxf 2 ?1.02.0ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design table 28. gmii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit output lv dd /2 r l = 50 z 0 = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 33 ethernet interface and mii management 8.2.3.1 mii transmit ac timing specifications table 29 provides the mii transmit ac timing specifications. figure 12 shows the mii transmit ac timing diagram. figure 12. mii transmit ac timing diagram 8.2.3.2 mii receive ac timing specifications table 30 provides the mii receive ac timing specifications. table 29. mii transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx 2 ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise (20%-80%) t mtxr 2 1.0 ? 4.0 ns tx_clk data clock fall (80%-20%) t mtxf 2 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. table 30. mii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx 2 ?400? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 34 freescale semiconductor ethernet interface and mii management figure 13 provides the ac test load for etsec. figure 13. etsec ac test load figure 14 shows the mii receive ac timing diagram. figure 14. mii receive ac timing diagram 8.2.4 tbi ac timing specifications this section describes the tbi trans mit and receive ac timing specifications. rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise (20%-80%) t mrxr 2 1.0?4.0ns rx_clk clock fall time (80%-20%) t mrxf 2 1.0?4.0ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. table 30. mii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 35 ethernet interface and mii management 8.2.4.1 tbi transmit ac timing specifications table 31 provides the tbi transmit ac timing specifications. figure 15 shows the tbi transmit ac timing diagram. figure 15. tbi transmit ac timing diagram table 31. tbi transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t ttx ?8.0? ns gtx_clk duty cycle t ttxh /t ttx 47 ? 53 % tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ? ? ns tcg[9:0] hold time from gtx_clk going high t ttkhdx 3 1.0 ? ? ns gtx_clk rise (20%?80%) t ttxr 2 ?1.02.0ns gtx_clk fall time (80%?20%) t ttxf 2 ?1.02.0ns ec_gtx_clk125 clock rise time (20%-80%) t g125r ?1.02.0ns ec_gtx_clk125 clock fall time (80%-20%) t g125f ?1.02.0ns ec_gtx_clk125 duty cycle t g125h /t g125 45 ? 55 ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. gtx_clk tcg[9:0] t ttxr t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx t ttxf
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 36 freescale semiconductor ethernet interface and mii management 8.2.4.2 tbi receive ac timing specifications table 32 provides the tbi receive ac timing specifications. figure 16 shows the tbi receive ac timing diagram. figure 16. tbi receive ac timing diagram table 32. tbi receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit pma_rx_clk[0:1] clock period t trx ? 16.0 ? ns pma_rx_clk[0:1] skew t sktrx 7.5 ? 8.5 ns pma_rx_clk[0:1] duty cycle t trxh /t trx 40 ? 60 % rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.5 ? ? ns pma_rx_clk[0:1] clock rise time (20%-80%) t trxr 2 0.7 ? 2.4 ns pma_rx_clk[0:1] clock fall time (80%-20%) t trxf 2 0.7 ? 2.4 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. guaranteed by design. pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 37 ethernet interface and mii management 8.2.5 tbi single-clock mode ac specifications when the etsec is configured for tbi modes, all cloc ks are supplied from external sources to the relevant etsec interface. in single-clock tbi mode, when tbicon[clksel] = 1 a 125-mhz tbi receive clock is supplied on tsec n tsecn_rx_clk pin (no receive clock is used on tsec n _tx_clk in this mode, whereas for the dual-clock mode this is the pma1 receive clock). the 125-mhz transmit clock is applied on the tsec_gtx_clk125 pin in all tbi modes. a summary of the single-clock tbi mode ac specifications for receive appears in table 33 . a timing diagram for tbi receive appears in figure 17 . . figure 17. tbi single-clock mode receive ac timing diagram 8.2.6 rgmii and rtbi ac timing specifications table 34 presents the rgmii and rtbi ac timing specifications. table 33. tbi single-clock mode receive ac timing specification parameter/condition symbol min typ max unit rx_clk clock period t trr 7.5 8.0 8.5 ns rx_clk duty cycle t trrh 40 50 60 % rx_clk peak-to-peak jitter t trrj ??250ps rise time rx_clk (20%?80%) t trrr ?1.02.0ns fall time rx_clk (80%?20%) t trrf ?1.02.0ns rcg[9:0] setup time to rx_clk rising edge t trrdv 2.0??ns rcg[9:0] hold time to rx_clk rising edge t trrdx 1.0??ns table 34. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt 5 ?500 6 0 500 6 ps data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock period duration 3 t rgt 5 7.2 8.0 8.8 ns t trr t trrh t trrf t trrr rx_clk rcg[9:0] valid data t trrdx t trrdv
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 38 freescale semiconductor ethernet interface and mii management duty cycle for 10base-t and 100base-tx 3, 4 t rgth /t rgt 5 40 50 60 % rise time (20%?80%) t rgtr 5 ?0.751.5ns fall time (20%?80%) t rgtf 5 ?0.751.5ns ec_gtx_clk125 clock rise time (20%-80%) t g125r ?0.751.5ns ec_gtx_clk125 clock fall time (80%-20%) t g125f ?0.751.5ns ec_gtx_clk125 duty cycle 6 t g125h /t g125 47 53 ns notes: 1. note that, in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. guaranteed by characterization 6. ec_gtx_clk125 is used to generate gtx_clk for the et sec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosen from 47/53% as long as the phy device can tolerate the duty cycle generated by the etsec gtx_clk. table 34. rgmii and rtbi ac timing specifications (continued) at recommended operating conditions with lv dd of 2.5 v 5%.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 39 ethernet interface and mii management figure 18 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 18. rgmii and rtbi ac timing and multiplexing diagrams 8.2.7 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 8.2.7.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 35 . table 35. rmii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit ref_clk clock period t rmt 15.0 20.0 25.0 ns ref_clk duty cycle t rmth 35 50 65 % ref_clk peak-to-peak jitter t rmtj ? ? 250 ps rise time ref_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmtf 1.0 ? 2.0 ns gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 40 freescale semiconductor ethernet interface and mii management figure 19 shows the rmii transmit ac timing diagram. figure 19. rmii transmit ac timing diagram 8.2.7.2 rmii receive ac timing specifications ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 1.0 ? 10.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 36. rmii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit ref_clk clock period t rmr 15.0 20.0 25.0 ns ref_clk duty cycle t rmrh 35 50 65 % ref_clk peak-to-peak jitter t rmrj ? ? 250 ps rise time ref_clk (20%?80%) t rmrr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup time to ref_clk rising edge t rmrdv 4.0 ? ? ns table 35. rmii transmit ac timing specifications (continued) at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 41 ethernet interface and mii management figure 20 provides the ac test load for etsec. figure 20. etsec ac test load figure 21 shows the rmii receive ac timing diagram. figure 21. rmii receive ac timing diagram 8.3 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 36. rmii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit output z 0 = 50 lv dd /2 r l = 50 ref_clk rxd[1:0] t rmrdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdv valid data
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 42 freescale semiconductor ethernet interface and mii management 8.3.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 37 . 8.3.2 mii management ac electrical characteristics table 38 provides the mii management ac timing specifications. table 37. mii management dc electrical characteristics parameters symbol min max unit supply voltage 3.3 v ov dd 3.13 3.47 v output high voltage (ov dd = min, i oh = ?1.0 ma) v oh 2.10 ov dd + 0.3 v output low voltage (ov dd = min, i ol = 1.0 ma) v ol gnd 0.50 v input high voltage v ih 2.0 ? v input low voltage v il ?0.90v input high current (ov dd = max, v in 1 = 2.1 v) i ih ?40 a input low current (ov dd = max, v in 1 = 0.5 v) i il ?600 ? a note: 1. the symbol v in , in this case, represents the ov in symbols referenced in ta b l e 2 and ta b l e 3 . table 38. mii management ac timing specifications parameters symbol min max unit notes mdc frequency f mdc ?2.5mhz2
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 43 ethernet interface and mii management figure 22 shows the mii management ac timing diagram. figure 22. mii management interface timing diagram mdc period t mdc 400 ? ns 2 mdc clock pulse width high t mdch 32 ? ns ? mdc to mdio delay t mdkhdx (16*t plb_clk )-3 (16*t plb_clk )+3 ns 3, 5 mdio to mdc setup time t mddvkh 5?ns? mdio to mdc hold time t mddxkh 0?ns? mdc rise time t mdcr ?10ns4 mdc fall time t mdcf ?10ns4 note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. ieee 802.3 standard specifies that the max mdc frequency to be 2.5mhz. the frequency is programmed through miimcfg[mgmtclk]. 3. this parameter is dependent on the platform clock speed. the delay is equal to 16 platform clock periods +/-3ns. with a platform clock of 333mhz, the min/max delay is 48ns +/- 3ns. 4. guaranteed by design 5. t plb_clk is the platform (ccb) clock period. 6. mdc to mdio data valid t mdkhdv is a function of clock period and max delay time (t mdkhdx ). (min setup time = cycle time ? max delay). table 38. mii management ac timing specifications (continued) parameters symbol min max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 44 freescale semiconductor local bus 9 local bus this section describes the dc and ac electrical speci fications for the local bus interface of the mpc8568. 9.1 local bus dc electrical characteristics table 39 provides the dc electrical characteristics for the local bus interface operating at bv dd = 3.3 v dc. table 40 provides the dc electrical characteristics for the local bus interface operating at bv dd = 2.5 v dc. table 39. local bus dc electrical characteristics (3.3 v dc) parameter symbol min max unit high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = bv dd ) i in ?5 a high-level output voltage (bv dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.4 v note: 1. the symbol v in , in this case, represents the bv in symbol referenced in ta b l e 2 and ta b l e 3 . table 40. local bus dc electrical characteristics (2.5 v dc) parameter symbol min max unit high-level input voltage v ih 1.70 bv dd + 0.3 v low-level input voltage v il ?0.3 0.7 v input current (v in 1 = 0 v or v in = bv dd ) i ih ?10 a i il ?15 high-level output voltage (bv dd = min, i oh = ?1 ma) v oh 2.0 ? v low-level output voltage (bv dd = min, i ol = 1 ma) v ol ?0.4 v note: 1. the symbol v in , in this case, represents the bv in symbol referenced in ta ble 2 and ta ble 3 .
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 45 local bus 9.2 local bus ac electrical specifications table 41 describes the timing parameters of the local bus interface at bv dd = 3.3 v. for information about the frequency range of local bus see section 23.1, ?clock ranges .? table 41. local bus timing parameters (bv dd = 3.3 v)?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % ? lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 8 input setup to local bus clock (except lgta /lupwait) t lbivkh1 1.8 ? ns 3, 4 lgta /lupwait input setup to local bus clock t lbivkh2 1.7 ? ns 3, 4 input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.0 ? ns 3, 4 lgta /lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?3.0ns? local bus clock to data valid for lad/ldp t lbkhov2 ?3.2ns3 local bus clock to address valid for lad t lbkhov3 ?3.2ns3 local bus clock to lale assertion t lbkhov4 ?3.2ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.7 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.7 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.5ns5 local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.5ns5 note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. 8. guaranteed by design.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 46 freescale semiconductor local bus table 42 describes the timing parameters of the local bus interface at bv dd = 2.5 v. figure 23 provides the ac test load for the local bus. table 42. local bus timing parameters (bv dd = 2.5 v)?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % ? lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 8 input setup to local bus clock (except lgta /upwait) t lbivkh1 1.9 ? ns 3, 4 lgta /lupwait input setup to local bus clock t lbivkh2 1.8 ? ns 3, 4 input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.1 ? ns 3, 4 lgta /lupwait input hold from local bus clock t lbixkh2 1.1 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?3.0ns? local bus clock to data valid for lad/ldp t lbkhov2 ?3.2ns3 local bus clock to address valid for lad t lbkhov3 ?3.2ns3 local bus clock to lale assertion t lbkhov4 ?3.2ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.8 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.8 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.6ns5 local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.6ns5 note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered thr ough the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. 8. guaranteed by design.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 47 local bus figure 23. local bus ac test load note pll bypass mode is required when lbiu frequency is at or below 83 mhz. when lbiu operates above 83 mhz, lbiu pll is recommended to be enabled. figure 24 to figure 29 show the local bus signals. figure 24. local bus signals (pll enabled) table 43 describes the timing parameters of the local bus interface at bv dd = 3.3 v with pll disabled. table 43. local bus timing parameters?pll bypassed parameter symbol 1 min max unit notes local bus cycle time t lbk 12 ? ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % ? output z 0 = 50 bv dd /2 r l = 50 () ()
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 48 freescale semiconductor local bus internal launch/capture clock to lclk delay t lbkhkt 2.3 4.4 ns 8 input setup to local bus clock (except lgta /lupwait) t lbivkh1 6.2 ? ns 4, 5 lgta /lupwait input setup to local bus clock t lbivkl2 6.1 ? ns 4, 5 input hold from local bus clock (except lgta /lupwait) t lbixkh1 ?1.8 ? ns 4, 5 lgta /lupwait input hold from local bus clock t lbixkl2 ?1.3 ? ns 4, 5 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbklov1 ?-0.3ns? local bus clock to data valid for lad/ldp t lbklov2 ?-0.1ns4 local bus clock to address valid for lad t lbklov3 ?0ns4 local bus clock to lale assertion t lbklov4 ?0ns4 output hold from local bus clock (except lad/ldp and lale) t lbklox1 ?3.7 ? ns 4 output hold from local bus clock for lad/ldp t lbklox2 ?3.7 ? ns 4 local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ?0.2ns7 local bus clock to output high impedance for lad/ldp t lbkloz2 ?0.2ns7 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for pll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. 4. all signals are measured from bvdd/2 of the rising edge of local bus clock for pll bypass mode to 0.4 x bvdd of the signal in question for 3.3-v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered thr ough the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. 9. guaranteed by design. table 43. local bus timing parameters?pll bypassed (continued) parameter symbol 1 min max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 49 local bus figure 25. local bus signals (pll bypass mode) note in pll bypass mode, lclk[n] is the inverted version of the internal clock with the delay of t lbkhkt. in this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock with the exception of lgta /lupwait (which is captured on the rising edge of the internal clock). output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkl2 t lbivkl2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt t lbklov4 lupwait
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 50 freescale semiconductor local bus figure 26. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 gpcm mode input signal: lgta
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 51 local bus figure 27. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 4 (pll bypass mode) t lbivkh1 t lbixkl2 internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 lclk t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 52 freescale semiconductor local bus figure 28. local bus signals, gpcm/upm signal s for lccr[clkdiv] = 8 or 16 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] gpcm mode input signal: lgta
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 53 local bus figure 29. local bus signals, gpcm/upm signals for lccr[clkdiv] = 8 or 16 (pll bypass mode) t lbixkl2 t lbivkh1 internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] lclk t lbklov1 t lbkloz1 t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 54 freescale semiconductor jtag 10 jtag this section describes the dc and ac electrical specifications for the ieee std 1149.1? (jtag) interface of the mpc8568e. 10.1 jtag dc electrical characteristics table provides the dc electrical spec ifications for the ieee 1149.1 (jtag) interface of the mpc8568e. 10.2 jtag ac electrical characteristics table 45 provides the jtag ac timing specifications as defined in figure 31 through figure 33 . table 44. jtag dc electrical characteristics parameter symbol condition min max unit output high voltage v oh i oh = -6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.5ov dd + 0.3 v input low voltage v il ?-0.30.8 v input current i in 0 < v in < ov dd ? 10 ua table 45. jtag ac timing specifications (independent of sysclk) 1 at recommended operating conditions (see ta b l e 3 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr & t jtgf 02ns6 trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 30 30 ? ? ns 5
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 55 jtag figure 30 provides the ac test load for tdo and the boundary-scan outputs. figure 30. ac test load for the jtag interface figure 31 provides the jtag clock input timing diagram. figure 31. jtag clock input timing diagram figure 32 provides the trst timing diagram. figure 32. trst timing diagram jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 30 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design table 45. jtag ac timing specifications (independent of sysclk) 1 (continued) at recommended operating conditions (see ta b l e 3 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 56 freescale semiconductor i 2 c figure 33 provides the boundary-scan timing diagram. figure 33. boundary-scan timing diagram 11 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interfaces of the mpc8568e. note that i 2 c2 is multiplexed with qe port c. pc[18] iic2_scl pc[19] iic2_sda 11.1 i 2 c dc electrical characteristics table 46 provides the dc electrical characteristics for the i 2 c interfaces. table 46. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.4v1 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns2 input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a3 vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 57 i 2 c 11.2 i 2 c ac electrical specifications table 47 provides the ac timing parameters for the i 2 c interfaces. capacitance for each i/o pin c i ?10pf? notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. refer to the mpc8568e powerquicc iii integrated communications processor reference manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 47. i 2 c ac electrical specifications at recommended operating conditions with ov dd of 3.3v 5%. all values refer to v ih (min) and v il (max) levels (see table 46 ). parameter symbol 1 min max unit scl clock frequency f i2c 0400khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns data input hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? ? s data output delay time t i2ovkl ?0.9 3 s set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v table 46. i 2 c dc electrical characteristics (continued) at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 58 freescale semiconductor i 2 c figure 30 provides the ac test load for the i 2 c. figure 34. i 2 c ac test load figure 35 shows the ac timing diagram for the i 2 c bus. figure 35. i 2 c bus ac timing diagram capacitive load for each bus line c b ?400pf note: 1.the symbols used for timing specifications herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. 2. as a transmitter, the mpc8568 provides a delay time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl to avoid unintended generation of start or stop condition. when the mpc8568 acts as the i 2 c bus master while transmitting, the mpc8568 drives both scl and sda. as long as the load on scl and sda are balanced, the mpc8568 would not cause unintended generation of start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if, under some rare condition, the 300 ns sda output delay time is required for the mpc8568 as transmitter, application note an2919 referred to in note 4 below is recommended. 3. the maximum t i2dxkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4.the requirements for i 2 c frequency calculation must be followed. refer to freescale application note an2919, determining the i 2 c frequency divider ratio for scl table 47. i 2 c ac electrical specifications (continued) at recommended operating conditions with ov dd of 3.3v 5%. all values refer to v ih (min) and v il (max) levels (see table 46 ). parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh ps
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 59 pci 12 pci this section describes the dc and ac electrical specifications for the pci bus of the mpc8568e. 12.1 pci dc electrical characteristics table 48 provides the dc electrical characteristics for the pci interface. 12.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus. note that the sysclk signal is used as the pci input clock. table 49 provides the pci ac timing specifications at 66 mhz. table 48. pci dc electrical characteristics 1 parameter symbol min max unit high-level input voltage v ih 0.5*ov dd ov dd + 0.3 v low-level input voltage v il ?0.5 0.3*ov dd v input current (v in 1 = 0 v or v in = v dd ) i in ? 10 a high-level output voltage (ov dd = min, i oh = ?500 a) v oh 0.9*ov dd ?v low-level output voltage (ov dd = max, i ol = 1500 a) v ol ?0.1*ov dd v notes: 1. the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 2 and ta b l e 3 . table 49. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes sysclk to output valid t pckhov ? 6.0 ns 2, 3 output hold from sysclk t pckhox 2.0 ? ns 2, 10 sysclk to output high impedance t pckhoz ? 14 ns 2, 4, 11 input setup to sysclk t pcivkh 3.0 ? ns 2, 5, 10 input hold from sysclk t pcixkh 0 ? ns 2, 5, 10
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 60 freescale semiconductor pci figure 30 provides the ac test load for pci. figure 36. pci ac test load figure 37 shows the pci input ac timing conditions. figure 37. pci input ac timing measurement conditions hreset high to first frame assertion t pcrhfv 10 ? clocks 8, 11 notes: 1. note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. all pci signals are measured from ov dd /2 of the rising edge of pci_clk to 0.4 ov dd of the signal in question for 3.3-v pci signaling levels. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. input timings are measured at the pin. 6. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various specified frequencies. the system clock period must be kept within the minimum and maximum defined ranges. for values see section 23, ?clocking .? 7. the setup and hold time is with respect to the rising edge of hreset . 8. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci 2.2 local bus specifications . 9. the reset assertion timing requirement for hreset is 100 s. 10.guaranteed by characterization 11.guaranteed by design table 49. pci ac timing specifications at 66 mhz (continued) parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50 t pcivkh clk input t pcixkh
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 61 high-speed serial interfaces (hssi) figure 38 shows the pci output ac timing conditions. figure 38. pci output ac timing measurement condition 13 high-speed serial interfaces (hssi) the mpc8568e features one serializer/deserializer (serdes) interfaces to be used for high-speed serial interconnect applications. it can be used for pci express and/or serial rapidio data transfers. this section describes the common portion of serdes dc electrical specifications, which is the dc requirement for serdes reference clocks. the serdes data lane?s transmitter and receiver reference circuits are also shown. 13.1 signal terms definition the serdes utilizes differential signaling to transfer data across the serial link. this section defines terms used in the description and specification of differential signals. figure 39 shows how the signals are defined. for illustration purpose, only one serdes lane is used for description. the figure shows waveform for either a transmitter output (sd_tx and sd_tx ) or a receiver input (sd_rx and sd_rx ). each signal swings between a volts and b volts where a > b. using this waveform, the definitions are as follows. to simplify illustration, the following definitions assume that the serdes transmitter and receiver opera te in a fully symmetrical differential signaling environment. 1. single-ended swing the transmitter output signals and the receiver input signals sd_tx, sd_tx , sd_rx and sd_rx each have a peak-to-peak swing of a ? b volts. this is also referred as each signal wire?s single-ended swing. 2. differential output voltage, v od (or differential output swing ): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sd_tx ? v sd_tx . the v od value can be either positive or negative. 3. differential input voltage, v id (or differential input swing ): clk output delay t pckhov high-impedance t pckhoz output
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 62 freescale semiconductor high-speed serial interfaces (hssi) the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sd_rx ? v sd_rx . the v id value can be either positive or negative. 4. differential peak voltage , v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, v diffp = |a ? b| volts. 5. differential peak-to-peak , v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input si gnal is defined as differential peak-to-peak voltage, v diffp-p = 2*v diffp = 2 * |(a ? b)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. for example, the output differential peak-peak voltage can also be calculated as v tx-diffp-p = 2*|v od |. 6. common mode voltage, v cm the common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. in this example, for serdes output, v cm_out = v sd_tx + v sd_tx = (a + b) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system, the common mode voltage may often differ from one component?s output to the other?s input. sometimes, it may be even different between the receiver input and driver output circuits within the same com ponent. it is also referred as the dc offset in some occasion. figure 39. differential voltage definitions for transmitter or receiver to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 v and 2.0 v. us ing these values, the peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p, which is referred as the single-ended swing for each signal. in this example, since the differential signaling environment is fully symmetrical, the transmitter output?s differential swing (v od ) has the same amplitude as each signal?s single-ended swing. the differential output signal ranges differential swing, v id or v od = a ? b a volts b volts sd_tx or sd_rx sd_tx or sd_rx differential peak voltage, v diffp = |a ? b| differential peak-peak voltage, v diffpp = 2*v diffp (not shown) v cm = (a + b) / 2
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 63 high-speed serial interfaces (hssi) between 500 mv and ?500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p. 13.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clocks inputs are sd_ref_clk and sd_ref_clk . the following sections describe the serdes re ference clock requirement s and some application information. 13.2.1 serdes reference clock receiver characteristics figure 40 shows a receiver reference diagram of the serdes reference clocks. ? the supply voltage requirements for scorevdd and xvdd are specified in table 2 and table 3 . ? serdes reference clock receiver reference circuit structure ? the sd_ref_clk and sd_ref_clk are internally ac-coupled differential inputs as shown in figure 40 . each differential clock input (sd_ref_clk or sd_ref_clk ) has a 50- termination to scoregnd followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be eith er differential or single-ended. refer to the differential mode and single-ended mode descri ption below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differential i nputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to th e following bullet for more detail), since the input is ac-coupled on-chip. ? this current limitation sets the maximum common m ode input voltage to be less than 0.4v (0.4v/50 = 8ma) while the minimum common m ode input level is 0.1v above scoregnd. for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0ma to 16ma (0-0.8v), such that each phase of the differential input has a single-ended swing fro m 0v to 800mv with the common mode voltage at 400mv. ? if the device driving the sd_ref_clk and sd_ref_clk inputs cannot drive 50 ohms to scoregnd dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 64 freescale semiconductor high-speed serial interfaces (hssi) figure 40. receiver of serdes reference clocks 13.2.2 dc level requirement for serdes reference clocks the dc level requirement for the mpc8568e serdes reference clock inputs is different depending on the signaling mode used to connect the clock driver ch ip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the differential cloc k must be between 400mv and 1600mv differential peak-peak (or between 200mv and 800mv differentia l peak). in other words, each signal wire of the differential pair must have a single- ended swing less than 800mv and greater than 200mv. this requirement is the same for both external dc-coupled or ac-coupled connection. ? for external dc-coupled connection, as described in section 13.2.1 , the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mv and 400 mv. figure 41 shows the serdes reference clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common m ode voltage requirement for the clock driver. since the external ac-coupling capac itor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connec tion scheme has its common mode voltage set to scoregnd. each signal wire of the differentia l inputs is allowed to swing below and above the command mode voltage (scoregnd). figure 42 shows the serdes reference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can also be single-ended. the sd_ref_clk input amplitude (single-ended swing) must be between 400mv and 800mv peak-peak (from vmin to vmax) with sd_ref_clk either left unconnected or tied to ground. ? the sd_ref_clk input average volta ge must be between 200 and 400 mv. figure 43 shows the serdes reference clock input requirement for single-ended signaling mode. ? to meet the input amplitude requirement, the re ference clock inputs might need to be dc or ac-coupled externally. for the best noise performance, the reference of the clock could be dc input amp 50 50 sd_ref_clk sd_ref_clk
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 65 high-speed serial interfaces (hssi) or ac-coupled into the unused phase (sd_ref_clk ) through the same source impedance as the clock input (sd_ref_clk) in use. figure 41. differential reference clock input dc requirements (external dc-coupled) figure 42. differential reference clock input dc requirements (external ac-coupled) figure 43. single-ended reference clock input dc requirements sd_ref_clk sd_ref_clk vmax < 800 mv vmin > 0v 100 mv < vcm < 400 mv 200 mv < input amplitude or differential peak < 800 mv sd_ref_clk sd_ref_clk vcm 200 mv < input amplitude or differential peak < 800 mv vmax < vcm + 400 mv vmin > vcm ? 400 mv sd_ref_clk sd_ref_clk 400 mv < sd_ref_clk input amplitude < 8 00 mv 0v
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 66 freescale semiconductor high-speed serial interfaces (hssi) 13.2.3 interfacing with other differential signaling levels ? with on-chip termination to scoregnd, the differential reference clocks inputs are hcsl (high-speed current steering logic) compatible dc-coupled. ? many other low voltage differen tial type outputs like lvds (low voltage differential signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 to 400 mv) for dc-coupled connection. ? lvpecl outputs can produce signal with too large amplitude and may need to be dc-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. note figure 44 to figure 47 below are for conceptual reference only. due to the fact that clock driver chip's inte rnal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. they might also vary from one vendor to the other. therefore, freescale semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. the system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the mpc8568 serdes reference clock receiver requirement provided in this document.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 67 high-speed serial interfaces (hssi) figure 44 shows the serdes reference clock connection reference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible with mpc8568 serdes reference clock input?s dc requirement. figure 44. dc-coupled differential connection with hcsl clock driver (reference only) figure 45 shows the serdes reference clock connection reference circuits for lvds type clock driver. since lvds clock driver?s common mode voltage is higher than the mpc8568 serdes reference clock input?s allowed range (100 to 400mv), ac-coupled connection scheme must be used. it assumes the lvds output driver features 50- termination resistor. it also assumes that the lvds transmitter establishes its own common mode level without rely ing on the receiver or other external component. figure 45. ac-coupled differential connection with lvds clock driver (reference only) 50 50 sd_ref_clk sd_ref_clk clock driver 100 differential pwb trace clock driver vendor dependent source termination resistor serdes refer. clk receiver clock driver clk_out clk_out hcsl clk driver chip 33 33 total 50 . assume clock driver?s output impedance is about 16 . mpc8568e clk_out 50 50 sd_ref_clk sd_ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvds clk driver chip 10 nf 10 nf mpc8568e
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 68 freescale semiconductor high-speed serial interfaces (hssi) figure 46 shows the serdes reference clock connection refe rence circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and output swing) are incompatible with mpc8568 serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 46 assumes that the lvpecl clock driver?s output impedance is 50 . r1 is used to dc-bias the lvpecl outputs prior to ac-coupling. its value could be ranged from 140 to 240 depending on clock driver vendor?s requirement. r2 is used together with the serdes reference clock receiver?s 50- termination resistor to attenuate the lvpecl output?s differentia l peak level such that it meets the mpc8568 serdes reference clock?s differential input amplitude require ment (between 200mv and 800mv differential peak). for example, if the lvpecl output?s differential peak is 900mv and the desired serdes reference clock input amplitude is selected as 600mv, the atte nuation factor is 0.67, which requires r2 = 25 . consult clock driver chip manufacturer to verify whether this connection scheme is comp atible with a particular clock driver chip. figure 46. ac-coupled differential connection with lvpecl clock driver (reference only) 50 50 sd_ref_clk sd_ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 r1 mpc8568e r1 10 nf 10 nf
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 69 high-speed serial interfaces (hssi) figure 47 shows the serdes reference clock connection refe rence circuits for a single-ended clock driver. it assumes the dc levels of the clock driver are compatible with mpc8568e serdes reference clock input?s dc requirement. figure 47. single-ended connection (reference only) 13.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. phase noise less than 100 khz can be tracked by the pll and data recovery loops and is less of a problem. phase noise above 15 mhz is f iltered by the pll. the most problematic phase noise occurs in the 1?15 mhz range. the source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. the detailed ac requirements of the serdes reference clocks is defined by each interface protocol based on application usage. refer to the foll owing sections for detailed information: ? section 14.2, ?ac requirements for pci express serdes clocks ? ? section 15.2, ?ac requirements for serial rapidio sd_ref_clk and sd_ref_clk ? 13.2.4.1 spread spectrum clock sd_ref_clk/sd_ref_clk were designed to work with a spread spectrum clock (+0 to ?0.5% spreading at 30?33 khz rate is allowed), assuming both e nds have same reference clock. for better results, a source without significant unintended modulation should be used. 50 50 sd_ref_clk sd_ref_clk 100 differential pwb trace serdes refer. clk receiver clock driver clk_out single-ended clk driver chip mpc8568e 33 total 50 . assume clock driver?s output impedance is about 16 . 50
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 70 freescale semiconductor pci express 13.3 serdes transmitter and receiver reference circuits figure 48 shows the reference circuits for serdes data lane?s transmitter and receiver. figure 48. serdes transmitter and receiver reference circuits the dc and ac specification of serdes data lanes ar e defined in each interface protocol section below (pci express, serial rapid io or sgmii) in this document based on the application usage: ? section 14, ?pci express ? ? section 15, ?serial rapidio ? note that external ac coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. 14 pci express this section describes the dc and ac electrical specifications for the pci express bus of the mpc8568e. 14.1 dc requirements for pci express sd_ref_clk and sd_ref_clk for more information, see section 13, ?high-speed serial interfaces (hssi).? 14.2 ac requirements for pci express serdes clocks table 50 lists ac requirements. table 50. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typical max units notes t ref refclk cycle time ? 10 ? ns 1 t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ? ? 100 ps ? 50 50 receiver transmitter sd_tx n sd_txn sd_rxn sd_rx n 50 50
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 71 pci express 14.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. this is specified to allow bit rate clock sources with a +/? 300 ppm tolerance. 14.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of th e transport and data link layer please use the pci express base specification. rev. 1.0a document. 14.4.1 differential transmitter (tx) output table 51 defines the specifications for the differential output at all transmitters (txs). the parameters are specified at the component pins. t refpj phase jitter. deviation in edge location with respect to mean edge location ?50 ? 50 ps ? notes: 1. typical based on pci express specification 2.0. table 51. differential transmitter (tx) output specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. v tx-diffp-p differential peak-to-peak output voltage 0.8 ? 1.2 v v tx-diffp-p = 2*|v tx-d+ ? v tx-d- | see note 2. v tx-de-ratio de- emphasized differential output voltage (ratio) ?3.0 ?3.5 ?4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note 2. t tx-eye minimum tx eye width 0.70 ? ? ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? t tx-eye = 0.3 ui. see notes 2 and 3. t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median. ? ? 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2 and 3. t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 ? ? ui see notes 2 and 5 table 50. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typical max units notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 72 freescale semiconductor pci express v tx-cm-acp rms ac peak common mode output voltage ??20mvv tx-cm-acp = rms(|v txd+ + v txd- |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 see note 2 v tx-cm-dc-active- idle-delta absolute delta of dc common mode voltage during l0 and electrical idle 0 ? 100 mv |v tx-cm-dc (during l0) ? v tx-cm-idle-dc (during electrical idle) |<=100 mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [l0] v tx-cm-idle-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [electrical idle] see note 2. v tx-cm-dc-line-delta absolute delta of dc common mode between d+ and d? 0?25mv|v tx-cm-dc-d+ ? v tx-cm-dc-d- | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | see note 2. v tx-idle-diffp electrical idle differential peak output voltage 0?20mvv tx-idle-diffp = |v tx-idle-d+ -v tx-idle-d- | <= 20 mv see note 2. v tx-rcv-detect the amount of voltage change allowed during receiver detection ? ? 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note 6. v tx-dc-cm the tx dc common mode voltage 0 ? 3.6 v the allowed dc common mode voltage under any conditions. see note 6. i tx-short tx short circuit current limit ? ? 90 ma the total current the transmitter can provide when shorted to its ground t tx-idle-min minimum time spent in electrical idle 50 ? ? ui minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set ? ? 20 ui after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from l0. t tx-idle-to-diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition ? ? 20 ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle rl tx-diff differential return loss 10 ? ? db measured over 50 mhz to 1.25 ghz. see note 4 table 51. differential transmitter (tx) output specifications (continued) symbol parameter min nom max units comments
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 73 pci express 14.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 49 is specified using the passive compliance/test measurement load (see figure 51 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. rl tx-cm common mode return loss 6 ? ? db measured over 50 mhz to 1.25 ghz. see note 4 z tx-diff-dc dc differential tx impedance 80 100 120 tx dc differential mode low impedance z tx-dc transmitter dc impedance 40 ? ? required tx d+ as well as d- dc impedance during all states l tx-skew lane-to-lane output skew ? ? 500 + 2 ui ps static skew between any two transmitter lanes within a single link c tx ac coupling capacitor 75 ? 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. see note 8. t crosslink crosslink random timeout 0 ? 1 ms this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note 7. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance test load as shown in figure 51 and measured over any 250 consecutive tx uis. (also refer to the transmitter compliance eye diagram shown in figure 49 ) 3. a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as oppose d to the averaged time value. 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50 ohm probes?see figure 51 ). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20-80% at transmitter package pins into a test load as shown in figure 51 for both v tx-d+ and v tx-d- . 6. see section 4.3.1.8 of the pci express base specifications rev 1.0a 7. see section 4.2.6.3 of the pci express base specifications rev 1.0a 8. mpc8568e serdes transmitter does not have c tx built-in. an external ac coupling capacitor is required. table 51. differential transmitter (tx) output specifications (continued) symbol parameter min nom max units comments
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 74 freescale semiconductor pci express a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algorithm using a minimization merit function (that is, least squa res and median deviation fits). figure 49. minimum transmitter timing and voltage output compliance specifications 14.4.3 differential receiver (rx) input specifications table 52 defines the specifications for the differential i nput at all receivers (rxs). the parameters are specified at the component pins. table 52. differential receiver (rx) input specifications symbol parameter min nom max units comments ui unit interval 399.8 8 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. v rx-diffp-p differential peak-to-peak output voltage 0.175 ? 1.200 v v rx-diffp-p = 2*|v rx-d+ ? v rx-d- | see note 2.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 75 pci express t rx-eye minimum receiver eye width 0.4 ? ? ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 ? t rx-eye = 0.6 ui. see notes 2 and 3. t rx-eye-median-to-max -jitter maximum time between the jitter median and maximum deviation from the median. ? ? 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2, 3 and 7. v rx-cm-acp ac peak common mode input voltage ?? 150 mvv rx-cm-acp = |v rxd+ + v rxd- |/2 ? v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ + v rx-d- |/2 see note 2 rl rx-diff differential return loss 10 ? ? db measured over 50 mhz to 1.25 ghz with the d+ and d- lines biased at +300 mv and -300 mv, respectively. see note 4 rl rx-cm common mode return loss 6 ? ? db measured over 50 mhz to 1.25 ghz with the d+ and d- lines biased at 0 v. see note 4 z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential mode impedance. see note 5 z rx-dc dc input impedance 40 50 60 required rx d+ as well as d- dc impedance (50 20% tolerance). see notes 2 and 5. z rx-high-imp-dc powered down dc input impedance 200 k ? ? required rx d+ as well as d- dc impedance when the receiver terminations do not have power. see note 6. v rx-idle-det-diffp-p electrical idle detect threshold 65 ? 175 mv v rx-idle-det-diffp-p = 2*|v rx-d+ -v rx-d- | measured at the package pins of the receiver t rx-idle-det-diff- entertime unexpected electrical idle enter detect threshold integration time ? ? 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entering to signal an unexpected idle condition. table 52. differential receiver (rx) input specifications (continued) symbol parameter min nom max units comments
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 76 freescale semiconductor pci express 14.5 receiver compliance eye diagrams the rx eye diagram in figure 50 is specified using the passive compliance/test measurement load (see figure 51 ) in place of any real pci express rx component. note: in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 51 ) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci expr ess component. the degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real pci express component to vary in impedance fr om the compliance/test measurement load. the input receiver eye diagram is implementation specific a nd is not specified. rx component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 50 ) expected at the input receiver based on some adequate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. l tx-skew total skew ? ? 20 ns skew across all lanes on a link. this includes variation in the length of skp ordered set (for example, com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 51 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 50 ). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db with the d+ line bias ed to 300 mv and the d- line biased to -300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 ohms to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50 ohm probes?see figure 51 ). note: that the series capacitors ctx is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5 ms transition time before receiver termination values must be met on all un-configured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on w hen it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algo rithm using a minimization merit function. least squares and median deviation fits have worked well with experimental and simulated data. table 52. differential receiver (rx) input specifications (continued) symbol parameter min nom max units comments
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 77 pci express the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note the reference impedance for return loss measurements is 50. to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50. probes?see figure 51 ). note that the series capacitors, ctx, are optional for the return loss measurement. figure 50. minimum receiver eye timing and voltage compliance specification 14.5.1 compliance test and measurement load the ac timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 51 . note the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exac tly matched in length at the package pin boundary.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 78 freescale semiconductor serial rapidio figure 51. compliance test/measurement load 15 serial rapidio this section describes the dc and ac electrical specifications for the rapidio interface of the mpc8568e, for the lp-serial physical layer. the electrical specifications cover both single and multiple-lane links. two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ra nging from simple board-to-board interconnect to driving two connectors across a backplane. a single rece iver specification is given that will accept signals from both the short run and long run transmitter specifications. the short run transmitter should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. this covers the case where connections are made to a mezzanine (daughter) card. the minimum swings of the short run specification reduce the overall power used by the transceivers. the long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. this allows a user to drive signals acr oss two connectors and a backplane. the specifications allow a distance of at least 50 cm at all baud rates. all unit intervals are specified with a toleranc e of +/? 100 ppm. the worst case frequency difference between any transmit and receive clock will be 200 ppm. to ensure interoperability between drivers and receivers of different vendors and technologies, ac coupling at the receiver input must be used. 15.1 dc requirements for serial rapidio sd_ref_clk and sd_ref_clk for more information, see section 13.2, ?serdes reference clocks.?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 79 serial rapidio 15.2 ac requirements for serial rapidio sd_ref_clk and sd_ref_clk table 50 lists ac requirements. 15.3 signal definitions lp-serial links use differential signaling. this se ction defines terms used in the description and specification of differential signals. figure 52 shows how the signals are defined. the figures show waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts where a > b. using these waveforms, the definitions are as follows: 7. the transmitter output signals and the receiver input signals td, td , rd and rd each have a peak-to-peak swing of a ? b volts 8. the differential output signal of the transmitter, v od , is defined as v td ?v td 9. the differential input signal of the receiver, v id , is defined as v rd -v rd 10. the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts 11. the peak value of the differential transmitte r output signal and the differential receiver input signal is a ? b volts 12. the peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (a ? b) volts figure 52. differential peak-peak voltage of transmitter or receiver table 53. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typical max units comments t ref refclk cycle time ? 10(8) ? ns 8 ns applies only to serial rapidio with 125-mhz reference clock t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ? ? 80 ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location ?40 ? 40 ps ? differential peak-peak = 2 * (a-b) a volts td or rd td or rd b volts
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 80 freescale semiconductor serial rapidio to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 v and 2.0 v. using these values, the peak-to-peak voltage swing of the signals td and td is 500 mv p-p. the differential output signa l ranges between 500 mv and ?500 mv. the peak differential voltage is 500 mv. the peak-to-peak differential voltage is 1000 mv p-p. 15.4 equalization with the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. effects such as inter-symbol interference (i si) or data dependent jitter are produced. this loss can be large enough to degrade the eye opening at the r eceiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. the most common equalization techniques that can be used are: ? a passive high pass filter network placed at the receiver. this is often referred to as passive equalization. ? the use of active circuits in the receiver. this is often referred to as adaptive equalization. 15.5 explanatory note on transmitter and receiver specifications ac electrical specifications are given for transmitter and receiver. long run and short run interfaces at three baud rates (a total of six cases) are described. the parameters for the ac electrical specifications are guided by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002. xaui has similar application goals to serial rapidio, as described in section 8.1. the goal of this standard is that electrical designs for serial rapidio can reuse electrical designs for xaui, suitably modified for applications at the baud intervals and reaches described herein. 15.6 transmitter specifications lp-serial transmitter electrical and timing specifications are stated in the text and tables of this section. the differential return loss, s11, of the transmitter in each case shall be better than ? ?10 db for (baud frequency)/10 < freq(f) < 625 mhz, and ? ?10 db + 10log(f/625 mhz) db for 625 mhz freq(f) baud frequency the reference impedance for the differential return loss measurements is 100 ohm resistive. differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. it is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. it is recommended that the timing skew at the output of an lp-serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2.50 gb and 15 ps at 3.125 gb.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 81 serial rapidio table 54. short run transmitter ac timing specifications?1.25 gbaud characteristic symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps +/? 100 ppm table 55. short run transmitter ac timing specifications?2.5 gbaud characteristic symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps +/? 100 ppm table 56. short run transmitter ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 82 freescale semiconductor serial rapidio multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps +/? 100 ppm table 57. long run transmitter ac timing specifications?1.25 gbaud characteristic symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps +/?100 ppm table 58. long run transmitter ac timing specifications?2.5 gbaud characteristic symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps +/? 100 ppm table 56. short run transmitter ac timing specifications?3.125 gbaud (continued) characteristic symbol range unit notes min max
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 83 serial rapidio for each baud rate at which an lp-serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown in figure 53 with the parameters specified in table 60 when measured at the output pins of the device and the device is driving a 100 ohm +/?5% differ ential resistive load. the output eye pattern of an lp-serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. figure 53. transmitter output compliance mask table 59. long run transmitter ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p ? deterministic jitter j d ? 0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps +/? 100 ppm 0 v diff min v diff max -vdiff min -vdiff max 0b1-b1 time in ui transmitter differential output voltage a1-a
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 84 freescale semiconductor serial rapidio 15.7 receiver specifications lp-serial receiver electrical and timing specifications are stated in the text and tables of this section. receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8 )*(baud frequency). this includes contributions from on-chip circuitry, the chip package and any off-chi p components related to the receiver. ac coupling components are included in this requirement. the refe rence impedance for return loss measurements is 100 resistive for differential return loss and 25 resistive for common mode. table 60. transmitter differential output eye diagram parameters transm itter type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud short range 250 500 0.175 0.39 1.25 gbaud long range 400 800 0.175 0.39 2.5 gbaud short range 250 500 0.175 0.39 2.5 gbaud long range 400 800 0.175 0.39 3.125 gbaud short range 250 500 0.175 0.39 3.125 gbaud long range 400 800 0.175 0.39 table 61. receiver ac timing specifications?1.25 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 ?12 ?? unit interval ui 800 800 ps +/? 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 54 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 85 serial rapidio table 62. receiver ac timing specifications?2.5 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 ?12 ?? unit interval ui 400 400 ps +/? 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 54 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. table 63. receiver ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 22 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 -12 ?? unit interval ui 320 320 ps +/- 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 54 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 86 freescale semiconductor serial rapidio figure 54. single frequency sinusoidal jitter limits 15.8 receiver eye diagrams for each baud rate at which an lp-serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate specification ( table 61 , table 62 , table 63 ) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver input compliance mask shown in figure 55 with the parameters specified in table . the eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 +/? 5% differential resistive load. 8.5 ui p-p 0.10 ui p-p sinusoidal jitter amplitude 22.1 khz 1.875 mhz 20 mhz frequency
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 87 serial rapidio figure 55. receiver input compliance mask 15.9 measurement and test requirements since the lp-serial electrical specification are guide d by the xaui electrical inte rface specified in clause 47 of ieee 802.3ae-2002, the measurement and test requirements defined here are similarly guided by clause 47. in addition, the cjpat test pattern defi ned in annex 48a of ieee 802.3ae-2002 is specified as the test pattern for use in eye pattern and j itter measurements. annex 48b of ieee 802.3ae-2002 is recommended as a reference for additiona l information on jitter test methods. 15.9.1 eye template measurements for the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the data pattern fo r template measurements is the table 64. receiver input compliance mask parameters exclusive of sinusoidal jitter receiver type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud 100 800 0.275 0.400 2.5 gbaud 100 800 0.275 0.400 3.125 gbaud 100 800 0.275 0.400 1 0 v diff max -v diff max v diff min -v diff min time (ui) receiver differential input voltage 0 ab 1-b1-a
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 88 freescale semiconductor serial rapidio continuous jitter test pattern (cjpat) defined in a nnex 48a of ieee 802.3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. four lane imple mentations shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specifi ed in annex 48a for transmission on lane 0. the amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10 -12 . the eye pattern shall be measured with ac coupling and the compliance template centered at 0 volts differential. the left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. the load for this test shall be 100 ohms resistive +/? 5% differential to 2.5 ghz. 15.9.2 jitter test measurements for the purpose of jitter measurement, the effects of a si ngle-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitte r. the data pattern for jitter measurements is the continuous jitter test pattern (cjpat) pattern defined in annex 48a of ieee 802.3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions , and opposite ends of the links shall use asynchronous clocks. four lane implementations shall use cjpat as defined in annex 48a. si ngle lane implementations shall use the cjpat sequence specified in annex 48a fo r transmission on lane 0. jitter shall be measured with ac coupling and at 0 volts differential. jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a ber curve such as that described in annex 48b of ieee 802.3ae. 15.9.3 transmit jitter transmit jitter is measured at the driver output when terminated into a load of 100 ohms resistive +/? 5% differential to 2.5 ghz. 15.9.4 jitter tolerance jitter tolerance is measured at the receiver using a jitte r tolerance test signal. this signal is obtained by first producing the sum of deterministic and random jitter de fined in and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in and . note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetr y (including jitter) about the mean zero crossing. eye template measurement requirements are as defined above. random jitter is ca librated using a high pass filter with a low frequency corner at 20 mhz and a 20 db/decade roll-off below this. the required sinusoidal jitter specified in is then added to the signal and the test load is replaced by the receiver being tested.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 89 timers 16 timers this section describes the dc and ac electrical specifications for the timers of the mpc8568e. 16.1 timers dc electrical characteristics table 65 provides the dc electrical characteristics for the mpc8568e timers pins, including tin, tout , tgate and rtc_clk. 16.2 timers ac timing specifications table 66 provides the timers input and output ac timing specifications. figure 56 provides the ac test load for the timers. figure 56. timers ac test load table 65. timers dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ?-0.30.8v input current i in 0 v v in ov dd ? 10 a table 66. timers input ac timing specifications 1 characteristic symbol 2 typ unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. timers inputs and outputs are asynchronous to any visible clock. timers outputs should be synchronized before use by any external synchronous logic. timers inputs are required to be valid for at least t tiwid ns to ensure proper operation output z 0 = 50 ov dd /2 r l = 50
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 90 freescale semiconductor pic 17 pic this section describes the dc and ac electrical speci fications for the external interrupt pins of the mpc8568e. 17.1 pic dc electrical characteristics table 67 provides the dc electrical characteristics for the external interrupt pins of the mpc8568e. 17.2 pic ac timing specifications table 68 provides the pic input and output ac timing specifications. table 67. pic dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ?-0.30.8v input current i in ?10 a output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins irq [0:7], irq_out , mcp_out , and ce ports interrupts. 2. irq_out and mcp_out are open drain pins, thus v oh is not relevant for those pins. table 68. pic input ac timing specifications 1 characteristic symbol 2 min unit ipic inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least tpiwid ns to ensure proper operation when working in edge triggered mode.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 91 spi 18 spi this section describes the dc and ac electrical specifications for the spi of the mpc8568e. 18.1 spi dc electrical characteristics table 69 provides the dc electrical characteristics for the mpc8568e spi. 18.2 spi ac timing specifications table 70 and provide the spi input and output ac timing specifications. figure 57 provides the ac test load for the spi. figure 57. spi ac test load table 69. spi dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ?-0.30.8v input current i in 0 v v in ov dd ? 10 a table 70. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs?master mode (internal clock) delay t nikhov 06ns spi outputs?slave mode (external clock) delay t nekhov 28ns spi inputs?master mode (internal clock) input setup time t niivkh 4?ns spi inputs?master mode (internal clock) input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhov symbolizes the nmsi outputs internal timing (ni) for the time t spi memory clock reference (k) goes from the high state (h) until outputs (o) are valid (v). output z 0 = 50 ov dd /2 r l = 50
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 92 freescale semiconductor tdm/si figure 58 through figure 59 represent the ac timing from table 72 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 58 shows the spi timing in slave mode (external clock). figure 58. spi ac timing in slave mode (external clock) diagram figure 59 shows the spi timing in master mode (internal clock). figure 59. spi ac timing in master mode (internal clock) diagram 19 tdm/si this section describes the dc and ac electrical specifications for the time-division-multiplexed and serial interface of the mpc8568e. 19.1 tdm/si dc electrical characteristics table 71 provides the dc electrical characteristics for the mpc8568e tdm/si. table 71. tdm/si dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v spiclk (input) t neixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 93 tdm/si 19.2 tdm/si ac timing specifications table 72 provides the tdm/si input and output ac timing specifications. figure 60 provides the ac test load for the tdm/si. figure 60. tdm/si ac test load figure 61 represents the ac timing from table 72 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. input low voltage v il ?-0.30.8v input current i in 0 v v in ov dd ? 10 a table 72. tdm/si ac timing specifications 1 characteristic symbol 2 min max unit tdm/si outputs?external clock delay t sekhov 211ns tdm/si outputs?external clock high impedance t sekhox 210ns tdm/si inputs?external clock input setup time t seivkh 5?ns tdm/si inputs?external clock input hold time t seixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sekhox symbolizes the tdm/si outputs external timing (se) for the time t tdm/si memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 71. tdm/si dc electrical characteristics (continued) characteristic symbol condition min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 94 freescale semiconductor utopia/pos figure 61 shows the tdm/si timing with external clock. figure 61. tdm/si ac timing (external clock) diagram 20 utopia/pos this section describes the dc and ac electrical sp ecifications for the utopia-packet over sonnet of the mpc8568e. 20.1 utopia/pos dc electrical characteristics table 73 provides the dc electrical char acteristics for the mpc8568e utopia. 20.2 utopia/pos ac timing specifications table 74 provides the utopia input and output ac timing specifications. table 73. utopia dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ?-0.30.8v input current i in 0 v v in ov dd ? 10 a table 74. utopia ac timing specifications 1 characteristic symbol 2 min max unit utopia outputs?internal clock delay t uikhov 08.0ns utopia outputs?external clock delay t uekhov 1 10.0 ns utopia outputs?internal clock high impedance t uikhox 08.0ns utopia outputs?external clock high impedance t uekhox 1 10.0 ns tdm/siclk (input) t seixkh t seivkh t sekhov input signals: tdm/si (see note) output signals: tdm/si (see note) t sekhox note: the clock edge is selectable on tdm/si
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 95 utopia/pos figure 62 provides the ac test load for the utopia. figure 62. utopia ac test load figure 63 through figure 64 represent the ac timing from table 74 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 63 shows the utopia timing with external clock. figure 63. utopia ac timing (external clock) diagram utopia inputs?internal clock input setup time t uiivkh 6?ns utopia inputs?external clock input setup time t ueivkh 4?ns utopia inputs?internal clock input hold time t uiixkh 0?ns utopia inputs?external clock input hold time t ueixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t uikhox symbolizes the utopia outputs internal timing (ui) for the time t utopia memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 74. utopia ac timing specifications 1 (continued) characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50 utopiaclk (input) t ueixkh t ueivkh t uekhov input signals: utopia output signals: utopia t uekhox
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 96 freescale semiconductor hdlc, bisync, transparent and synchronous uart figure 64 shows the utopia timing with internal clock. figure 64. utopia ac timing (internal clock) diagram 21 hdlc, bisync, transparent and synchronous uart this section describes the dc and ac electrical speci fications for the high level data link control (hdlc), bisync, transparent and synchronous uart of the mpc8568e. 21.1 hdlc, bisync, transparent and synchronous uart dc electrical characteristics table 75 provides the dc electrical characteristics for the mpc8568e hdlc, bisync, transparent and synchronous uart protocols. 21.2 hdlc, bisync, transparent and synchronous uart ac timing specifications table 76 provides the input and output ac timing specifications for hdlc, bisync, transparent and synchronous uart protocols. table 75. hdlc, bisync, transparent and synchronous uart dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ?-0.30.8v input current i in 0 v v in ov dd ? 10 a table 76. hdlc, bisync, transparent ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t hikhov 06.5ns outputs?external clock delay t hekhov 18ns utopiaclk (output) t uiixkh t uikhov input signals: utopia output signals: utopia t uiivkh t uikhox
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 97 hdlc, bisync, transparent and synchronous uart figure 65 provides the ac test load. figure 65. ac test load outputs?internal clock high impedance t hikhox 05.5ns outputs?external clock high impedance t hekhox 18ns inputs?internal clock input setup time t hiivkh 6?ns inputs?external clock input setup time t heivkh 4?ns inputs?internal clock input hold time t hiixkh 0?ns inputs?external clock input hold time t heixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 77. synchronous uart ac timing specifications characteristic symbol 2 min max unit outputs?internal clock delay t hikhov 011ns outputs?external clock delay t hekhov 114ns outputs?internal clock high impedance t hikhox 011ns outputs?external clock high impedance t hekhox 114ns inputs?internal clock input setup time t hiivkh 6?ns inputs?external clock input setup time t heivkh 8?ns inputs?internal clock input hold time t hiixkh 0?ns inputs?external clock input hold time t heixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 76. hdlc, bisync, transparent ac timing specifications 1 (continued) characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 98 freescale semiconductor hdlc, bisync, transparent and synchronous uart figure 66 through figure 67 represent the ac timing from table 76 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 66 shows the timing with external clock. figure 66. ac timing (external clock) diagram figure 67 shows the timing with internal clock. figure 67. ac timing (internal clock) diagram serial clk (input) t heixkh t heivkh t hekhov input signals: (see note) output signals: (see note) t hekhox note: the clock edge is selectable serial clk (output) t hiixkh t hikhov input signals: (see note) output signals: (see note) t hiivkh t hikhox note: the clock edge is selectable
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 99 package and pinout 22 package and pinout this section details package paramete rs, pin assignments, and dimensions. 22.1 package parameters for the mpc8568e fc-pbga the package parameters are as provided in the following list. the package type is 33mm 33mm, 1023 flip chip plastic ball grid array (fc-pbga). package outline 33 mm 33 mm interconnects 1023 pitch 1 mm module height 2.23 ? 2.75 mm solder balls 96.5% sn 3.5% ag ball diameter (typical) 0.6 mm 22.2 mechanical dimensions of the mpc8568e fc-pbga figure 68 shows the top view, bottom and side view of the mpc8568e 1023 fc-pbga package.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 100 freescale semiconductor package and pinout figure 68. top, bottom, side views 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. all dimensions are symmetric across the package center lines, unless dimensioned otherwise.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 101 package and pinout 4. maximum solder ball diameter measured parallel to datum a. 5. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 6. paralleusm measurement shall exclude any effect of mark on top surface of package 7. capacitors may not be present on all devices. 8. caution must be taken not to short capacitors or exposed metal capacitor pads on top of package. 22.3 pinout listings some of the non-qe signals are multiplexed with qe port pins, as follows: pc[0] uart_sout[1] pc[1] uart_rts [1] pc[2] uart_cts [1] pc[3] uart_sin[1] pc[11] irq[8] pc[12] irq[9]/dma_dreq [3] pc[13] irq[10]/dma_dack [3] pc[14] irq[11]/dma_ddone [3] pc[15] dma_dreq [1] pc[16] dma_dack [1] pc[17] dma_ddone [1] pc[18] iic2_scl pc[19] iic2_sda pd[28] uart_sout[1] pd[29] uart_rts [1] pd[30] uart_cts [1] pd[31] uart_sin[1] this applies to both mpc8568e and mpc8568e. note that for duart1, there are two options. duart0 is multiplexed with pci req/grant pins. pci_req [3] uart_cts [0] pci_req [4] uart_sin[0] pci_gnt [3] uart_rts [0] pci_gnt [4] uart_sout[0] for mpc8568e, gpio is multiplexed with the tsec2 interface: tsec2_txd[7:0] gpout[0:7]
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 102 freescale semiconductor package and pinout tsec2_rxd[7:0] gpin[0:7] other muxing includes: lcs [5] dma_dreq [2] lcs [6] dma_dack [2] lcs [7] dma_ddone [2] table 79 provides the pin-out listing for the mpc8568e 1023 fc-pbga package. table 78. mpc8568e pinout listing signal package pin number pin type power supply notes pci pci_ad[31:0] ae19, ag20, af19, ab20, ac20, ag21, ag22, ab21, af22, ah22, ae22, af20, ab22, ae20, ae23, aj23, aj24, af27, aj26, ae29, ah24, ad24, ae25, ae26, ah27, ag27, aj25, ae30, af26, ag26, af28, ah26 i/o ov dd ? pci_c_be [3:0] ac22, ad20, ae28, ah25 i/o ov dd ? pci_gnt [4:1] af29, ab18, ac18, ad18 o ov dd 5,9,35 pci_gnt0 ae18 i/o ov dd ? pci_irdy af23 i/o ov dd 2 pci_par aj22 i/o ov dd pci_perr af24 i/o ov dd 2 pci_serr ad22 i/o ov dd 2,4 pci_stop ae24 i/o ov dd 2 pci_trdy ak24 i/o ov dd 2 pci_req [4:1] ag29, aj27, ah29, ab17 i ov dd ? pci_req[0] ac17 i/o ov dd ? pci_clk am26 i ov dd 39 pci_devsel ak23 i/o ov dd 2 pci_frame ae21 i/o ov dd 2 pci_idsel ab19 i ov dd ? ddr sdram memory interface mdq[0:63] b22, c22, e20, a19, c23, a22, a20, c20, g22, e22, e16, f16, e23, f23, f17, h17, a18, a17, b16, c16, b19, c19, e17, a16, a13, a14, a12, c12, a15, b15, b13, c13, g12, g11, h8, f8, d13, f12, e9, f9, a7, b7, c5, e5, c8, e8, d6, a5, e6, g6, e1, f1, g7, e7, e2, d1, c4, a3, b1, c1, a4, b4, c2, d2 i/o gv dd ? mecc[0:7] c11, e11, d9, a8, d12, a11, a9, c9 i/o gv dd ? mdm[0:8] a21, e21, d18, b14, f11, a6, g5, a2, a10 o gv dd ?
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 103 package and pinout mdqs[0:8] d21, g20, c17, d14, e10, c6, f4, c3, c10 i/o gv dd ? mdqs [0:8] c21, g21, c18, d15, f10, c7, f5, d3, b10 i/o gv dd ? ma[0:15] k7, h7, l7, j8, k8, l10, h9, k9, h10, g10, l6, k10, k11, h3, j11, j12 ogv dd ? mba[0:2] k4, h6, l13 o gv dd ? mwe k3 o gv dd ? mcas l3 o gv dd ? mras k6 o gv dd ? mcke[0:3] l14, g13, k12, j13 o gv dd 11 mcs [0:3] j5, h2, k5, k2, o gv dd ? mck[0:5] g15, f20, e4, f14, e19, g3 o gv dd ? mck [0:5] g14, f19, e3, f13, e18, g2 o gv dd ? modt[0:3] g4, j1, j4, k1 o gv dd ? mdic[0:1] g1, h1 i/o gv dd 36 local bus controller interface lad[0:31] m26, c30, f31, l24, g26, d30, m25, l26, d29, g32, g28, k26, b32, m24, g29, l25, e29, j23, b30, a31, j24, k23, h25, h23, f26, c28, b29, e25, d26, g24, a29, e27, i/o bv dd ? ldp[0:3] g30, j26, h28, e26 i/o bv dd ? la[27] f29 o bv dd 5,9 la[28:31] h24, c32, f30, h26 o bv dd 5,7,9 lale g31 o bvdd 8 lbctl l27 o bvdd 8 lcs [0:4] m27, h32, j28, j30, b31 o bv dd ? lcs5 g25 i/o bv dd 1 lcs6 c29 o bv dd 1 lcs7 a30 o bv dd 1 lwe [0] h30 o bv dd 5,9 lwe [1] e28 o bv dd 5,9 lwe [2] e32 o bv dd 5,9 lwe [3] g27 o bv dd 5,9 lgpl0 e30 o bv dd 5,9 lgpl1 j27 o bv dd 5,9,46 lgpl2 d32 o bv dd 5,8,9 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 104 freescale semiconductor package and pinout lgpl3 j25 o bv dd 5,9 lgpl4 c25 i/o bv dd 49 lgpl5 f32 o bv dd 5,9 lcke c31 o bv dd ? lclk[0:2] c27, c26, d25 o bv dd ? lsync_in a28 i bv dd ? lsync_out a27 o bv dd ? dma dma_dack [0] am27 o ov dd 5,9,46 dma_dreq [0] ak28 i ov dd ? dma_ddone [0] ak26 o ov dd ? programmable interrupt controller ude ag32 i ov dd ? mcp af32 i ov dd ? irq[0:7] ad30, ag31, al30, af31, ad29, ak30, ag30, af30 iov dd ? irq_out ad28 o ov dd 2,4 interface ec_mdc ae17 o ov dd 5,9 ec_mdio af17 i/o ov dd ? gigabit reference clock ec_gtx_clk125 am14 i lv dd ? three-speed ethernet controller (gigabit ethernet 1) tsec1_rxd[7:0] ae14, am11, ak11, af11, aj14, aj13, ad12, ae13 ilv dd ? tsec1_txd[7] ah12 o lv dd 5, 9 tsec1_txd[6:1] al13, al11, ak13, ah13, ag11, ad13 o lv dd ? tsec1_txd[0] am13 o lv dd 5, 9 tsec1_col ag13 i lv dd ? tsec1_crs ab13 i/o lv dd 20 tsec1_gtx_clk ag12 o lv dd ? tsec1_rx_clk ae11 i lv dd ? tsec1_rx_dv ah11 i lv dd ? tsec1_rx_er am12 i lv dd ? table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 105 package and pinout tsec1_tx_clk aj11 i lv dd ? tsec1_tx_en ac13 o lv dd 30 tsec1_tx_er al12 o lv dd 5,9 three-speed ethernet controller (gigabit ethernet 2) tsec2_rxd[7:0] ac14, ad15, ab14, ah15, ad14, ah17, ae15, ac15 ilv dd ? tsec2_txd[7] am16 o lv dd 5, 9 tsec2_txd[6:1] aj15, aj17, af13, ak17, ah16, ag17 o lv dd ? tsec2_txd[0] al15 o lv dd 5, 9 tsec2_col ab15 i lv dd ? tsec2_crs ab16 i/o lv dd 20 tsec2_gtx_clk aj16 o lv dd ? tsec2_rx_clk ae16 i lv dd ? tsec2_rx_dv ag15 i lv dd ? tsec2_rx_er af15 i lv dd ? tsec2_tx_clk ah14 i lv dd ? tsec2_tx_en am15 o lv dd 30 tsec2_tx_er ak15 o lv dd ? i 2 c interface iic1_scl ae32 i/o ov dd 4,27 iic1_sda ad32 i/o ov dd 4,27 serdes sd_rx[0:7] l30, m32, n30, p32, u30, v32, w30, y32 i scorevdd 43,44 sd_rx [0:7] l29, m31, n29, p31, u29, v31, w29, y31 i scorevdd 43,44 sd_tx[0:7] p26, r24, t26, u24, w24, y26, aa24, ab26 o xv dd 44 sd_tx [0:7] p27, r25, t27, u25, w25, y27, aa25, ab27 o xv dd 44 sd_pll_tpd r32 o scorevdd 24 sd_rx_clk u28 i xv dd 41,44 sd_rx_frm_ctl v28 i xv dd 41,44 reserved v26 ? ? 48 reserved v27 ? ? 48 sd_ref_clk t32 i scorevdd 44 sd_ref_clk t31 i scorevdd 44 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 106 freescale semiconductor package and pinout quicc engine pa[0:4] m1, m2, m5, m4, m3 i/o ov dd 5,17 pa [ 5 ] n 3 i / o o v dd 29 pa[6:31] m6, m7, m8, n5, m10, n1, m11, m9, p1, n9, n7, r6, r2, p7, p5, r4, p3, p11, p10, p9, r8, r7, r5, r3, r1, t2 i/o ov dd ? pb[4:31] t1, r11, r9, t6, t5, t4, t3, u10, t9, t8, t7, u5, u3, u1, t11, v1, u11, u9, u7, v5, w4, v3, w2, v9, w8, v7, w6, w3 i/o ov dd ? pc[0:31] w1, v11, v10, w11, w9, w7, w5, y4, y3, y2, y1, y8, y7, y6, y5, aa1, y11, aa10, y9, aa9, aa7, aa5, aa3, ab3, ac2, ab1, aa11, ab7, ac6, ab5, ac4, ab9 i/o ov dd ? pd[4:31] ac8, ad1, ac1, ac7, ab10, ac5, ad3, ad2, ac3, ae4, af1, ae3, ae1, ad6, ag2, ag1, ad5, ad7, ad4, ah1, ak3, ad8, af5, am4, ac9, al2, ae5, af3 i/o ov dd ? pe[5:7] am6, al5, al9 i/o tv dd ? pe[8:10] am9, am10, al10 i/o tv dd 5 pe[11:19] aj9, ah10, am8, ak9, al7, al8, ah9, am7, ah8 i/o tv dd ? pe[20] ah6 i/o ov dd ? pe[21:23] am1, ae10, ag5 i/o ov dd 5 pe[24] aj1 i/o ov dd 5 pe[25:31] ah2, am2, ae9, ah5, al1, ad9, al4 i/o ov dd ? pf[7] ag9 i/o tv dd ? pf[8:10] af10, ak7, aj6 i/o tv dd 5 pf[11:19] ah7, af9, aj7, aj5, af7, ag8, ag7, am5, ak5 i/o tv dd ? pf[20] ak1 i/o ov dd ? pf[21:22] ah3, al3 i/o ov dd 5,33 pf[23:31] ab11, ae7, aj3, ac11, ag6, ag3, ah4, am3, ad11 i/o ov dd ? system control hreset al21 i ov dd ? hreset_req al23 o ov dd 29 sreset ak18 i ov dd ? ckstp_in al17 i ov dd ? ckstp_out am17 o ov dd 2,4 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 107 package and pinout debug trig_in al29 i ov dd ? trig_out am29 o ov dd 6,9,19 ,29 msrcid[0:1] ak29, aj29 o ov dd 5,6,9 msrcid[2:4] am28, al28, ak27 o ov dd 6,19,2 9 mdval aj28 o ov dd 6 clk_out af18 o ov dd 11 clock rtc ah20 i ov dd ? sysclk ak22 i ov dd ? jtag tck ah18 i ov dd ? tdi ah19 i ov dd 12 tdo aj18 o ov dd 11 tms ak19 i ov dd 12 trst ak20 i ov dd 12 dft l1_tstclk aj20 i ov dd 25 l2_tstclk aj19 i ov dd 25 lssd_mode ah31 i ov dd 25 test_sel aj31 i ov dd 25 thermal management therm0 ab30 ? ? 14 therm1 ab31 ? ? 14 power management asleep ak21 o ov dd 9,19,2 9 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 108 freescale semiconductor package and pinout power and ground signals gnd a23, a26, a32, b3, b6, b9, b12, b18, b21, b23, b24, b25, b26, b27, c15, c24, d5, d8, d11, d17, d20, d23, d24, d28, e13, e14, e24, e31, f3, f7, f15, f18, f22, f24, f27, g8, g16, g19, g23, h5, h12, h13, h15, h16, h18, h19, h21, h22, j2, j7, j10, j14, j15, j16, j17, j18, j19, j20, j21, j22, j29, j31, j32, k14, k15, k16, k17, k18, k19, k20, k21, k22, k24, l1, l4, l9, l12, l15, l16, l17, l18, l19, l20, l21, l22, l23, m12, m13, m18, m20, m21, m23, n4, n8, n11, n13, n15, n17, n19, n21, n23, p2, p6, p12, p14, p16, p18, p20, p22, p23, r10, r13, r15, r17, r19, r21, r23, t12, t14, t16, t18, t20, t22, t23, u4, u8, u13, u15, u17, u19, u21, u23, v2, v6, v12, v14, v16, v18, v20, v22, v23, w10, w13, w15, w17, w19, w21, w23, y12, y14, y16, y18, y20, y22, y23, aa4, aa8, aa12, aa13, aa15, aa17, aa19, aa21, aa22, aa23, ab2, ab6, ab12, ab23, ab29, ab32, ac10, ac23, ac24, ac25, ac28, ac29, ac30, ac31, ac32, ad16, ad17, ad19, ad21, ad25, ad26, ad27, ad31, ae8, ae12, af2, af4, af6, af16, af21, af25, ag10, ag14, ag18, ag24, ag28, ah23, aj4, aj8, aj12, aj21, aj30, aj32, ak2, ak10, ak16, ak32, al6, al14, al18, al19, al20, al22, al24, al25, al26, al31, al32, am19, am21, am23, am25, am30, am31, am32 ??? scoregnd k28, k29, k30, l28, l31, m28, m30, n32, p28, p30, r28, t29, u32, v30, w28, w31, y28, y29, aa29, aa30, aa32, ab28 ground for serdes receiver ?? xgnd n24, n26, p25, r27, t24, u26, v25, w27, y24, aa26, ab25, ac27 ground for serdes transmitter ?? ovdd n2, n6, n10, p4, p8, t10, u2, u6, v4, v8, y10, aa2, aa6, ab4, ab8, ac19, ac21, ad10, ad23, ae2, ae6, ae27, ae31, ag4, ag19, ag23, ag25, ah21, ah28, ah30, ah32, aj2, ak4, ak25, ak31, al27 power for pci and other standards (3.3v) ovdd ? lvdd ac12, ac16, af12, af14, ag16, ak12, ak14, al16 power for etsec1 and etsec2 (2.5v,3.3v) lv d d ? tvdd af8, aj10, ak6, ak8 power for qe ucc1 and ucc2 ethernet interface (2,5v,3.3v) tvdd ? table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 109 package and pinout gvdd b2, b5, b8, b11, b17, b20, c14, d4, d7, d10, d16, d19, d22, e12, e15, f2, f6, f21, g9, g17, g18, h4, h11, h14, h20, j3, j6, j9, k13, l2, l5, l8, l11 power for ddr1 and ddr2 dram i/o voltage (1.8v,2.5v) gvdd ? bvdd b28, d27, d31, f25, f28, h27, h29, h31, k25, k27 power for local bus (1.8v, 2.5v, 3.3v) bvdd ? vdd m14, m15, m19, m22, n12, n14, n16, n18, n20, n22, p13, p15, p17, p19, p21, r12, r14, r16, r18, r20, r22, t13, t15, t17, t19, t21, u12, u14, u16, u18, u20, u22, v13, v15, v17, v19, v21, w12, w14, w16, w18, w20, w22, y13, y15, y17, y19, y21, aa14, aa16, aa18, aa20 power for core (1.1) vdd ? scorevdd k31, l32, m29, n28, n31, p29, t28, t30, u31, v29, w32, y30, aa31 core power for serdes transceivers (1.1v) scorevdd ? xvdd n25, n27, p24, r26, t25, u27, v24, w26, y25, aa27, ab24, ac26 pad power for serdes transceivers (1.1v) xvdd ? av dd_lbiu a25 power for local bus pll (1.1v) ?26 av dd_pci am22 power for pci pll (1.1v) ?26 av dd_ce am18 power for qe pll (1.1v) ?26 av dd_core am24 power for e500 pll (1.1v) ?26 av dd_plat am20 power for ccb pll (1.1v) ?26 av dd_srds r29 power for srdspll (1.1v) ?26 agnd_srds r31 ground for srdspll ?? sensevdd m17 o v dd 13 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 110 freescale semiconductor package and pinout sensevss m16 ? ? 13 analog signals mvref a24 i reference voltage signal for ddr mvref ? sd_imp_cal_rx k32 i 200 to gnd ? sd_imp_cal_tx aa28 i 100 to gnd ? sd_pll_tpa r30 o ? 24 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 111 package and pinout notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller section, and is not mentioned in the dma section even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 4. this pin is an open drain signal. 5. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the processor is in th e reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 6. treat these pins as no connects (nc) unless using debug address functionality. 7. the value of la[28:31] during reset sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 23.2, ?ccb/sysclk pll ratio .? 8. the value of lale, lgpl2 and lbctl at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see the section 23.3, ?e500 core pll ratio .? 9. functionally, this pin is an output, but structurally it is an i/o because it either samples configuration input during reset or because it has other manufacturing test functions. this pin will therefore be described as an i/o for boundary scan. 11.this output is actively driven during reset rather than being three-stated during reset. 12.these jtag pins have weak internal pull-up p-fets that are always enabled. 13.these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 14.internal thermally sensitive resistor. these two pins are not esd protected. 17.. the value of pa[0:4] during reset set the qe clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 23.4, ?qe/sysclk pll ratio .? 19. if this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a s afe state during reset. 20. this pin is only an output in fifo mode when used as rx flow control. 24. do not connect. 25.these are test signals for factory use only and must be pulled up (100 - 1 k) to ovdd for normal machine operation. 26. independent supplies derived from board vdd. 27. recommend a pull-up resistor (~1 k.) be placed on this pin to ov dd . 29. the following pins must not be pulled down during power-on reset: hreset_req, trig_out/ready/quiesce, msrcid[2:4], asleep, pa[5] table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 112 freescale semiconductor package and pinout table 79 provides the pin-out listing for the MPC8567E 1023 fc-pbga package. 30. this pin requires an external 4.7-k pull-down resistor to prevent phy from seeing a valid transmit enable before it is actively driven. 33. pf[21:22] are multiplexed as cfg_dram_type[0:1]. they must be valid at power-up, even before hreset assertion. 35. when a pci block is disabled, either the por config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other pci device connected on the pci bus, or leave the pci n _ad pins as "no connect" or terminated through 2?10 k pull-up resistors with the default of internal arbiter if the pci n _ad pins are not connected to any other pci device. the pci block will drive the pci n _ad pins if it is configured to be the pci arbiter?through por config pins?irrespective of whether it is disabled via the devdisr register or not. it may cause contention if there is any other pci device connected on the bus. 36.mdic[0] is grounded through an 18.2- precision 1% resistor and mdic[1] is connected to gv dd through an 18.2- precision 1% resistor. these pins are used for automatic calibration of the ddr ios. 39. if pci is configured as pci asynchronous mode, a valid clock must be provided on pin pci_clk . otherwise the processor will not boot up. 41.these pins should be tied to scoregnd through a 300 ohm resistor if the high speed interface is used. 43. it is highly recommended that unused sd_rx/sd_rx lanes should be powered down with lane_x_pd. otherwise the receivers will burn extra power and the internal circuitry may develop long term reliability problems. 44. see section 25.9, ?guidelines for high-speed interface termination .? 46. must be high during hreset . it is recommended to leave the pin open during hreset since it has internal pullup resistor. 47. must be pulled down with 4.7-k resistor. 48. this pin must be left no connect. 49. a pull-up on lgpl4 is required for systems that boot from local bus (gpcm)-controlled nor flash. table 79. MPC8567E pinout listing signal package pin number pin type power supply notes pci pci_ad[31:0] ae19, ag20, af19, ab20, ac20, ag21, ag22, ab21, af22, ah22, ae22, af20, ab22, ae20, ae23, aj23, aj24, af27, aj26, ae29, ah24, ad24, ae25, ae26, ah27, ag27, aj25, ae30, af26, ag26, af28, ah26 i/o ov dd ? pci_c_be [3:0] ac22, ad20, ae28, ah25 i/o ov dd ? pci_gnt [4:1] af29, ab18, ac18, ad18 o ov dd 5,9,35 pci_gnt0 ae18 i/o ov dd ? pci_irdy af23 i/o ov dd 2 pci_par aj22 i/o ov dd ? pci_perr af24 i/o ov dd 2 pci_serr ad22 i/o ov dd 2,4 pci_stop ae24 i/o ov dd 2 pci_trdy ak24 i/o ov dd 2 table 78. mpc8568e pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 113 package and pinout pci_req [4:1] ag29, aj27, ah29, ab17 i ov dd ? pci_req[0] ac17 i/o ov dd ? pci_clk am26 i ov dd 39 pci_devsel ak23 i/o ov dd 2 pci_frame ae21 i/o ov dd 2 pci_idsel ab19 i ov dd ? ddr sdram memory interface mdq[0:63] b22, c22, e20, a19, c23, a22, a20, c20, g22, e22, e16, f16, e23, f23, f17, h17, a18, a17, b16, c16, b19, c19, e17, a16, a13, a14, a12, c12, a15, b15, b13, c13, g12, g11, h8, f8, d13, f12, e9, f9, a7, b7, c5, e5, c8, e8, d6, a5, e6, g6, e1, f1, g7, e7, e2, d1, c4, a3, b1, c1, a4, b4, c2, d2 i/o gv dd ? mecc[0:7] c11, e11, d9, a8, d12, a11, a9, c9 i/o gv dd ? mdm[0:8] a21, e21, d18, b14, f11, a6, g5, a2, a10 o gv dd ? mdqs[0:8] d21, g20, c17, d14, e10, c6, f4, c3, c10 i/o gv dd ? mdqs [0:8] c21, g21, c18, d15, f10, c7, f5, d3, b10 i/o gv dd ? ma[0:15] k7, h7, l7, j8, k8, l10, h9, k9, h10, g10, l6, k10, k11, h3, j11, j12 ogv dd ? mba[0:2] k4, h6, l13 o gv dd ? mwe k3 o gv dd ? mcas l3 o gv dd ? mras k6 o gv dd ? mcke[0:3] l14, g13, k12, j13 o gv dd 11 mcs [0:3] j5, h2, k5, k2, o gv dd ? mck[0:5] g15, f20, e4, f14, e19, g3 o gv dd ? mck [0:5] g14, f19, e3, f13, e18, g2 o gv dd ? modt[0:3] g4, j1, j4, k1 o gv dd ? mdic[0:1] g1, h1 i/o gv dd 36 local bus controller interface lad[0:31] m26, c30, f31, l24, g26, d30, m25, l26, d29, g32, g28, k26, b32, m24, g29, l25, e29, j23, b30, a31, j24, k23, h25, h23, f26, c28, b29, e25, d26, g24, a29, e27, i/o bv dd ? ldp[0:3] g30, j26, h28, e26 i/o bv dd ? la[27] f29 o bv dd 5,9 la[28:31] h24, c32, f30, h26 o bv dd 5,7,9 table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 114 freescale semiconductor package and pinout lale g31 o bvdd 8 lbctl l27 o bvdd 8 lcs [0:4] m27, h32, j28, j30, b31 o bv dd ? lcs5 g25 i/o bv dd 1 lcs6 c29 o bv dd 1 lcs7 a30 o bv dd 1 lwe [0] h30 o bv dd 5,9 lwe [1] e28 o bv dd 5,9 lwe [2] e32 o bv dd 5,9 lwe [3] g27 o bv dd 5,9 lgpl0 e30 o bv dd 5,9 lgpl1 j27 o bv dd 5,9,46 lgpl2 d32 o bv dd 5,8,9 lgpl3 j25 o bv dd 5,9 lgpl4 c25 i/o bv dd 49 lgpl5 f32 o bv dd 5,9 lcke c31 o bv dd ? lclk[0:2] c27, c26, d25 o bv dd ? lsync_in a28 i bv dd ? lsync_out a27 o bv dd ? dma dma_dack [0] am27 o ov dd 5,9,47 dma_dreq [0] ak28 i ov dd ? dma_ddone [0] ak26 o ov dd ? programmable interrupt controller ude ag32 i ov dd ? mcp af32 i ov dd ? irq[0:7] ad30, ag31, al30, af31, ad29, ak30, ag30, af30 iov dd ? irq_out ad28 o ov dd 2,4 gpio gpin[0:7] ac14, ad15, ab14, ah15, ad14, ah17, ae15, ac15 ilv dd ? table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 115 package and pinout gpout[0:7] am16, aj15, aj17, af13, ak17, ah16, ag17, al15 olv dd ? i 2 c interface iic1_scl ae32 i/o ov dd 4,27 iic1_sda ad32 i/o ov dd 4,27 serdes sd_rx[0:7] l30, m32, n30, p32, u30, v32, w30, y32 i scorevdd 43,44 sd_rx [0:7] l29, m31, n29, p31, u29, v31, w29, y31 i scorevdd 43,44 sd_tx[0:7] p26, r24, t26, u24, w24, y26, aa24, ab26 o xv dd 44 sd_tx [0:7] p27, r25, t27, u25, w25, y27, aa25, ab27 o xv dd 44 sd_pll_tpd r32 o scorevdd 24 sd_rx_clk u28 i xv dd 41,44 sd_rx_frm_ctl v28 i xv dd 41,44 reserved v26 ? ? 48 reserved v27 ? ? 48 sd_ref_clk t32 i scorevdd 44 sd_ref_clk t31 i scorevdd 44 quicc engine pa[0:4] m1, m2, m5, m4, m3 i/o ov dd 5,17 pa [ 5 ] n 3 i / o ov dd 29 pa[6:31] m6, m7, m8, n5, m10, n1, m11, m9, p1, n9, n7, r6, r2, p7, p5, r4, p3, p11, p10, p9, r8, r7, r5, r3, r1, t2 i/o ov dd ? pb[4:31] t1, r11, r9, t6, t5, t4, t3, u10, t9, t8, t7, u5, u3, u1, t11, v1, u11, u9, u7, v5, w4, v3, w2, v9, w8, v7, w6, w3 i/o ov dd ? pc[0:31] w1, v11, v10, w11, w9, w7, w5, y4, y3, y2, y1, y8, y7, y6, y5, aa1, y11, aa10, y9, aa9, aa7, aa5, aa3, ab3, ac2, ab1, aa11, ab7, ac6, ab5, ac4, ab9 i/o ov dd ? pd[4:31] ac8, ad1, ac1, ac7, ab10, ac5, ad3, ad2, ac3, ae4, af1, ae3, ae1, ad6, ag2, ag1, ad5, ad7, ad4, ah1, ak3, ad8, af5, am4, ac9, al2, ae5, af3 i/o ov dd ? pe[5:7] am6, al5, al9 i/o tv dd ? pe[8:10] am9, am10, al10 i/o tv dd 5 pe[11:19] aj9, ah10, am8, ak9, al7, al8, ah9, am7, ah8 i/o tv dd ? table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 116 freescale semiconductor package and pinout pe[20] ah6 i/o ov dd ? pe[21:23] am1, ae10, ag5 i/o ov dd 5 pe[24] aj1 i/o ov dd 5 pe[25:31] ah2, am2, ae9, ah5, al1, ad9, al4 i/o ov dd ? pf[7] ag9 i/o tv dd ? pf[8:10] af10, ak7, aj6 i/o tv dd 5 pf[11:19] ah7, af9, aj7, aj5, af7, ag8, ag7, am5, ak5 i/o tv dd ? pf[20] ak1 i/o ov dd ? pf[21:22] ah3, al3 i/o ov dd 5,33 pf[23:31] ab11, ae7, aj3, ac11, ag6, ag3, ah4, am3, ad11 i/o ov dd ? system control hreset al21 i ov dd ? hreset_req al23 o ov dd 29 sreset ak18 i ov dd ? ckstp_in al17 i ov dd ? ckstp_out am17 o ov dd 2,4 debug trig_in al29 i ov dd ? trig_out am29 o ov dd 6,9,19, 29 msrcid[0:1] ak29, aj29 o ov dd 5,6,9 msrcid[2:4] am28, al28, ak27 o ov dd 6,19,29 mdval aj28 o ov dd 6 clk_out af18 o ov dd 11 clock rtc ah20 i ov dd ? sysclk ak22 i ov dd ? jtag tck ah18 i ov dd ? tdi ah19 i ov dd 12 tdo aj18 o ov dd 11 tms ak19 i ov dd 12 trst ak20 i ov dd 12 table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 117 package and pinout dft l1_tstclk aj20 i ov dd 25 l2_tstclk aj19 i ov dd 25 lssd_mode ah31 i ov dd 25 test_sel aj31 i ov dd 25 thermal management therm0 ab30 ? ? 14 therm1 ab31 ? ? 14 power management asleep ak21 o ov dd 9,19,29 power and ground signals gnd a23, a26, a32, b3, b6, b9, b12, b18, b21, b23, b24, b25, b26, b27, c15, c24, d5, d8, d11, d17, d20, d23, d24, d28, e13, e14, e24, e31, f3, f7, f15, f18, f22, f24, f27, g8, g16, g19, g23, h5, h12, h13, h15, h16, h18, h19, h21, h22, j2, j7, j10, j14, j15, j16, j17, j18, j19, j20, j21, j22, j29, j31, j32, k14, k15, k16, k17, k18, k19, k20, k21, k22, k24, l1, l4, l9, l12, l15, l16, l17, l18, l19, l20, l21, l22, l23, m12, m13, m18, m20, m21, m23, n4, n8, n11, n13, n15, n17, n19, n21, n23, p2, p6, p12, p14, p16, p18, p20, p22, p23, r10, r13, r15, r17, r19, r21, r23, t12, t14, t16, t18, t20, t22, t23, u4, u8, u13, u15, u17, u19, u21, u23, v2, v6, v12, v14, v16, v18, v20, v22, v23, w10, w13, w15, w17, w19, w21, w23, y12, y14, y16, y18, y20, y22, y23, aa4, aa8, aa12, aa13, aa15, aa17, aa19, aa21, aa22, aa23, ab2, ab6, ab12, ab23, ab29, ab32, ac10, ac23, ac24, ac25, ac28, ac29, ac30, ac31, ac32, ad16, ad17, ad19, ad21, ad25, ad26, ad27, ad31, ae8, ae12, af2, af4, af6, af16, af21, af25, ag10, ag14, ag18, ag24, ag28, ah23, aj4, aj8, aj12, aj21, aj30, aj32, ak2, ak10, ak16, ak32, al6, al14, al18, al19, al20, al22, al24, al25, al26, al31, al32, am19, am21, am23, am25, am30, am31, am32 ??? scoregnd k28, k29, k30, l28, l31, m28, m30, n32, p28, p30, r28, t29, u32, v30, w28, w31, y28, y29, aa29, aa30, aa32, ab28 ground for serdes receiver ?? xgnd n24, n26, p25, r27, t24, u26, v25, w27, y24, aa26, ab25, ac27 ground for serdes transmitter ?? table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 118 freescale semiconductor package and pinout ovdd n2, n6, n10, p4, p8, t10, u2, u6, v4, v8, y10, aa2, aa6, ab4, ab8, ac19, ac21, ad10, ad23, ae2, ae6, ae27, ae31, ag4, ag19, ag23, ag25, ah21, ah28, ah30, ah32, aj2, ak4, ak25, ak31, al27 power for pci and other standards (3.3v) ovdd ? lvdd ac12, ac16, af12, af14, ag16, ak12, ak14, al16 power for gpio lv d d ? tvdd af8, aj10, ak6, ak8 power for qe ucc1 and ucc2 ethernet interface (2,5v,3.3v) tvdd ? gvdd b2, b5, b8, b11, b17, b20, c14, d4, d7, d10, d16, d19, d22, e12, e15, f2, f6, f21, g9, g17, g18, h4, h11, h14, h20, j3, j6, j9, k13, l2, l5, l8, l11 power for ddr1 and ddr2 dram i/o voltage (1.8v,2.5v) gvdd ? bvdd b28, d27, d31, f25, f28, h27, h29, h31, k25, k27 power for local bus (1.8v, 2.5v, 3.3v) bvdd ? vdd m14, m15, m19, m22, n12, n14, n16, n18, n20, n22, p13, p15, p17, p19, p21, r12, r14, r16, r18, r20, r22, t13, t15, t17, t19, t21, u12, u14, u16, u18, u20, u22, v13, v15, v17, v19, v21, w12, w14, w16, w18, w20, w22, y13, y15, y17, y19, y21, aa14, aa16, aa18, aa20 power for core (1.1) vdd ? scorevdd k31, l32, m29, n28, n31, p29, t28, t30, u31, v29, w32, y30, aa31 core power for serdes transceivers (1.1v) scorevdd ? xvdd n25, n27, p24, r26, t25, u27, v24, w26, y25, aa27, ab24, ac26 pad power for serdes transceivers (1.1v) xvdd ? av dd_lbiu a25 power for local bus pll (1.1v) ?26 av dd_pci am22 power for pci pll (1.1v) ?26 av dd_ce am18 power for qe pll (1.1v) ?26 table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 119 package and pinout av dd_core am24 power for e500 pll (1.1v) ?26 av dd_plat am20 power for ccb pll (1.1v) ?26 av dd_srds r29 power for srdspll (1.1v) ?26 agnd_srds r31 ground for srdspll ? sensevdd m17 o v dd 13 sensevss m16 ? ? 13 analog signals mvref a24 i reference voltage signal for ddr mvref ? sd_imp_cal_rx k32 i 200 to gnd ? sd_imp_cal_tx aa28 i 100 to gnd ? sd_pll_tpa r30 o ? 24 reserved pins reserved ae17, ah12, al13, al11, ak13, ah13, ag11, ad13, am13, ag12, ac13, al12, aj16, am15, ak15 n/a n/a 42 reserved af17, am14, ae14, am11, ak11, af11, aj14, aj13, ad12, ae13, ag13, ab13, ae11, ah11, am12, aj11, ab15, ab16, ae16, ag15, af15, ah14 n/a n/a 45 table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 120 freescale semiconductor package and pinout notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller section, and is not mentioned in the dma section even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 4. this pin is an open drain signal. 5. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the processor is in th e reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 6. treat these pins as no connects (nc) unless using debug address functionality. 7. the value of la[28:31] during reset sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 23.2, ?ccb/sysclk pll ratio .? 8. the value of lale, lgpl2 and lbctl at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see the section 23.3, ?e500 core pll ratio .? 9. functionally, this pin is an output, but structurally it is an i/o because it either samples configuration input during reset or because it has other manufacturing test functions. this pin will therefore be described as an i/o for bo undary scan. 11.this output is actively driven during reset rather than being three-stated during reset. 12.these jtag pins have weak internal pull-up p-fets that are always enabled. 13.these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 14.internal thermally sensitive resistor. these two pins are not esd protected. 17.. the value of pa[0:4] during reset set the qe clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 23.4, ?qe/sysclk pll ratio .? 19. if this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a s afe state during reset. 20. this pin is only an output in fifo mode when used as rx flow control. 24. do not connect. 25.these are test signals for factory use only and must be pulled up (100 - 1 k) to ovdd for normal machine operation. 26. independent supplies derived from board vdd. 27. recommend a pull-up resistor (~1 k.) be placed on this pin to ov dd . 29. the following pins must not be pulled down during power-on reset: hreset_req, trig_out/ready/quiesce, msrcid[2:4], asleep, pa[5]. table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 121 clocking 23 clocking this section describes the pll configuration of the mpc8568e. note that the platform clock is identical to the core complex bus (ccb) clock. 23.1 clock ranges table 80 provides the clocking specifications for the processor cores and table 81 provides the clocking specifications for the ddr/ddr2 memory bus. table 82 provides the clocking specifications for the local bus. 30. this pin requires an external 4.7-k pull-down resistor to prevent phy from seeing a valid transmit enable before it is actively driven. 33. pf[21:22] are multiplexed as cfg_dram_type[0:1]. they must be valid at power-up, even before hreset assertion. 35. when a pci block is disabled, either the por config pin that selects between internal and external arbiter must be pulled d own to select external arbiter if there is any other pci device connected on the pci bus, or leave the pci n _ad pins as "no connect" or terminated through 2?10 k pull-up resistors with the default of internal arbiter if the pci n _ad pins are not connected to any other pci device. the pci block will drive the pci n _ad pins if it is configured to be the pci arbiter?through por config pins?irrespective of whether it is disabled via the devdisr register or not. it may cause contention if there is any other pci device connected on the bus. 36.mdic[0] is grounded through an 18.2- precision 1% resistor and mdic[1] is connected to gv dd through an 18.2- precision 1% resistor. these pins are used for automatic calibration of the ddr ios. 39. if pci is configured as pci asynchronous mode, a valid clock must be provided on pin pci_clk . otherwise the processor will not boot up. 41.these pins should be tied to scoregnd through a 300 ohm resistor if the high speed interface is used. 43. it is highly recommended that unused sd_rx/sd_rx lanes should be powered down with lane_x_pd. otherwise the receivers will burn extra power and the internal circuitry may develop long term reliability problems. 44. see section 25.9, ?guidelines for high-speed interface termination .? 46. must be high during hreset . it is recommended to leave the pin open during hreset since it has internal pullup resistor. 47. must be pulled down with 4.7-k resistor. 48. this pin must be left no connect. 49. a pull-up on lgpl4 is required for systems that boot from local bus (gpcm)-controlled nor flash. table 80. processor core clocking specifications characteristic maximum processor core frequency unit notes 800 mhz 1000 mhz 1333 mhz min max min max min max e500 core processor frequency 533 800 533 1000 533 1333 mhz 1, 2 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 23.2, ?ccb/sysclk pll ratio ,? and section 23.3, ?e500 core pll ratio ,? for ratio settings. 2.)the minimum e500 core frequency is based on the minimum platform frequency of 333 mhz. table 79. MPC8567E pinout listing (continued) signal package pin number pin type power supply notes
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 122 freescale semiconductor clocking 23.2 ccb/sysclk pll ratio the ccb clock is the clock that drives the e500 core complex bus (ccb) and is also called the platform clock. the frequency of the ccb is set using the following reset signals, as shown in table 83 : ? sysclk input signal ? binary value on la[28:31] at power up note that there is no default for this pll ratio; these signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the ccb bus frequency, since the ccb frequency must equal the ddr data rate. for specifications on the pci_clk, refer to the pci 2.2 specification. table 81. ddr/ddr2 memory bu s clocking specifications characteristic maximum processor core frequency unit notes 800, 1000, 1333 mhz min max ddr/ddr2 memory bus clock frequency 166 266 mhz 1, 2 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 core frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. 2. the memory bus clock speed is half the ddr/ddr2 data rate, hence, half the platform clock frequency. table 82. local bus clocking specifications characteristic maximum processor core frequency unit notes 800, 1000, 1333 mhz min max local bus clock speed (for local bus controller) 25 166 mhz 1 notes: 1. the local bus clock speed on lclk[0:2] is determined by ccb clock divided by the local bus pll ratio programmed in lccr[clkdiv]. see the reference manual for more information on this. table 83. ccb clock ratio binary value of la[28:31] signals ccb:sysclk ratio binary value of la[28:31] signals ccb:sysclk ratio 0000 16:1 1000 8:1 0001 reserved 1001 9:1 0010 2:1 1010 10:1 0011 3:1 1011 reserved 0100 4:1 1100 12:1
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 123 clocking 23.3 e500 core pll ratio table 84 describes the clock ratio between the e500 core complex bus (ccb)platform and the e500 core clock. this ratio is determined by the binary valu e of lbctl, lale and lgpl2 at power up, as shown in table 84 . 23.4 qe/sysclk pll ratio the qe clock is defined by a multiplier and divisor app lied to the sysclk input signal, as shown in the following equation: qe clock = sysclk * cfg_ce_pll[0:4]. the multiplier and divisor is determined by the binary value of pa[0:4] at power up. 0101 5:1 1101 20:1 0110 6:1 1110 reserved 0111 reserved 1111 reserved table 84. e500 core to ccb clock ratio binary value of lbctl, lale, lgpl2 signals e500 core:ccb clock ratio binary value of lbctl, lale, lgpl2 signals e500 core:ccb clock ratio 000 4:1 100 2:1 001 9:2 101 5:2 010 reserved 110 3:1 011 3:2 111 7:2 table 85. qe clock multiplier cfg_ce_pll[0:4] binary value of pa[0:4] signals cfg_ce_pll[0:4] binary value of pa[0:4] signals cfg_ce_pll[0:4] 0_0000 16 1_0000 16 0_0001 reserved 1_0001 17 0_0010 2 1_0010 18 0_0011 3 1_0011 19 0_0100 4 1_0100 20 0_0101 5 1_0101 21 0_0110 6 1_0110 22 0_0111 7 1_0111 23 table 83. ccb clock ratio (continued) binary value of la[28:31] signals ccb:sysclk ratio binary value of la[28:31] signals ccb:sysclk ratio
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 124 freescale semiconductor clocking 23.5 frequency options 23.5.1 sysclk to platform frequency options table 86 shows the expected frequency values for the platform frequency when using a ccb clock to sysclk ratio in comparison to the memory bus clock speed. 0_1000 8 1_1000 24 0_1001 9 1_1001 25 0_1010 10 1_1010 26 0_1011 11 1_1011 27 0_1100 12 1_1100 28 0_1101 13 1_1101 29 0_1110 14 1_1110 30 0_1111 15 1_1111 31 table 86. frequency options of sysclk with respect to memory bus speeds ccb clock to sysclk ratio sysclk (mhz) 16.66 25 33.33 41.66 66.66 83 100 111 133.33 166 platform /ccb clock frequency (mhz) 2 333 3 333 400 500 4 333 400 445 533 5 333 415 500 6 400 500 8 333 533 9 375 10 333 417 12 400 500 16 400 533 20 333 500 table 85. qe clock multiplier cfg_ce_pll[0:4] (continued) binary value of pa[0:4] signals cfg_ce_pll[0:4] binary value of pa[0:4] signals cfg_ce_pll[0:4]
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 125 thermal 23.5.2 minimum platform frequency requirements for pci express, srio, pci interfaces operation for proper pci express operation, the ccb clock frequency must be greater than: note that the ?pci express link width? in the above equation refers to the negotiated link width as the result of pci express link training, which may or ma y not be the same as the link width por selection. for proper serial rapidio operation, the ccb clock frequency must be greater than: for proper pci operation in synchronous mode, the minimum ccb:sysclk ratio is 6:1. 24 thermal this section describes the thermal specifications of the mpc8568e. 24.1 thermal characteristics table 87 provides the package thermal characteristics. 24.2 thermal management information this section provides thermal management information for the flip chip plastic ball grid array (fc-pbga) package for air-cooled applications. proper ther mal control design is pr imarily dependent on the table 87. package thermal characteristics characteristic symbol value unit notes junction-to-ambient natural convection on single layer board (1s) r ja 21 c/w 1, 2 junction-to-ambient natural convection on four layer board (2s2p) r ja 17 c/w 1, 2 junction-to-ambient (@200 ft/min or 1 m/s) on single layer board (1s) r ja 16 ?c/w c/w 1, 2 junction-to-ambient (@200 ft/min or 1 m/s) on four layer board (2s2p) r ja 13 ?c/w c/w 1, 2 junction-to-board r jb 9?c/w c/w 3 junction-to-case r jc <0.1 ?c/w c/w 4 notes 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2. per jedec jesd51-6 with the board horizontal. 3. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (mil spec-883, method 1012.1) with the calculated case temperature. actual thermal resistance is less than 0.1 c/w. 527 mhz pci express link width () 8 ---------------------------------------------------------------------------------------------- 20.80 () serial rapidio interface frequency () serial rapidio link width () 64 ------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 126 freescale semiconductor thermal system-level design?the heat sink, airflow, and th ermal interface material. the recommended attachment method to the heat sink is illustrated in figure 69 . the heat sink should be attached to the printed-circuit board with the spring force centered over the die. this spring force should not exceed 10 pounds force. figure 69. package exploded cross-sectional view with several heat sink options the system board designer can choose between several types of heat sinks to place on the device. there are several commercially-available heat sinks from the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com advanced thermal solutions 781-769-2800 89 access road #27. norwood, ma02062 internet: www.qats.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-millennium.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity , spatial volume, mass, attachment method, assembly, and cost. several heat sinks offered by aavid thermalloy, advanced thermal solutions, alpha novatech, ierc, and thermal interface material heat sink fc-pbga package heat sink clip printed-circuit board die
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 127 thermal millennium electronics offer different heat sink-to-ambient thermal resistances, that will allow the mpc8568e to function in various environments. 24.2.1 recommended thermal model for system thermal modeling, the mpc8568e thermal model without a lid is shown in figure 70 . the substrate is modeled as a block 33x33x1.18 mm with an in-plane conductivity of 24 w/mk and a through-plane conductivity of 0.92 w/mk. the solder balls and air are modeled as a single block 33x33x0.58 mm with an in-plane conductivity of 0. 034 w/mk and a through plane conductivity of 12.2 w/mk. the die is modeled as 8.2x12.1 mm with a thickness of 0.75 mm. the bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate assuming a conductivity of 5.3 w/m?k in the thickness dimension of 0.07 mm. the die is centered on the substrate. the thermal model uses approximate dimensions to reduce grid. see the case outline for actual dimensions. figure 70. mpc8568e thermal model 24.2.2 internal package conduction resistance for the packaging technology, shown in table 87 , the intrinsic internal conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance heat source substrate top view of model (not to scale) x y conductivity value unit die (8.2 12.1 0.75mm) silicon temperature dependent w/(m k) bump/underfill (8.2 12.1 0.75 mm) collapsed resistance k z 5.3 substrate (33 33 1.18 mm) k x 24 k y 24 k z 0.92 soldera and air (33 33 0.58 mm) k x 0.034 k y 0.034 k z 12.2 substrate solder/air die bump/underfill side view of model (not to scale) z
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 128 freescale semiconductor thermal ? the die junction-to-board thermal resistance figure 71 depicts the primary heat transfer path for a pa ckage with an attached heat sink mounted to a printed-circuit board. figure 71. package with heat sink mounted to a printed-circuit board the heat sink removes most of the heat from the device. heat generated on the active side of the chip is conducted through the silicon, then through the heat si nk attach material (or thermal interface material), and finally to the heat sink. the junction-to-case ther mal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 24.2.3 thermal interface materials a thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 72 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a join t with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. the bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 69 ). therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance)
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 129 thermal figure 72. thermal performance of select thermal interface materials the system board designer can choose between severa l types of thermal interface. there are several commercially-available thermal inte rfaces provided by the following vendors: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dow.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 130 freescale semiconductor system design information thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 25 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8568e. 25.1 system clocking this device includes six plls, as follows: 1. the platform pll generates the platform clock from the externally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio configuration bits as described in section 23.2, ?ccb/sysclk pll ratio.? 2. the e500 core pll generates the core clock usi ng the platform clock as the input. the frequency ratio between the e500 core clock and the platform clock is selected using the e500 pll ratio configuration bits as described in section 23.3, ?e500 core pll ratio .? 3. the pci pll generates the clocking for the pci bus 4. the local bus pll generates the clock for the local bus. 5. there is a pll for the serdes block. 6. qe pll generates the qe clock fr om the externally supplied sysclk. 25.2 power supply design and sequencing 25.2.1 pll power supply filtering each of the plls listed above is provided w ith power through independent power supply pins (av dd_plat , av dd_core , av dd_pci , av dd_lbiu , and av dd_srds , av dd_ce respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits pe r pll power supply as illustrated in figure 73 , one to each of the av dd type pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 131 system design information each circuit should be placed as close as possible to the specific av dd type pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd type pin, which is on the periphery of 1023fc-pbga the footprint, without the inductance of vias. figure 73 shows the pll power supply filter circuits for all plls except serdes pll. figure 73. mpc8568e pll power supply filter circuit the av dd_srds signal provides power for the analog portions of the serdes pll. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in following figure. for maximum effectiveness, the filter circuit is placed as closely as possible to the av dd_srds and agnd_srds ball to ensure it filters out as much noise as possible. the 0.003-f capacitor is closest to the ball, followed by the 2.2-f capacitors, and finally the 1 ohm resistor to the board supply plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all traces should be kept short, wide and direct. figure 74. serdes pll power supply filter note the following: ?av dd_srds should be a filtered version of scorevdd. ? the transmitter output signals on the serdes interface are fed from the xv dd power plan. ? power: xvdd consumes less than 300mw. scorevdd + av dd_srds consumes less than 750mw. 25.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. mpc8568e system, and the device itself requires a clean , tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , tv dd , bv dd , ov dd , gv dd , and lv dd pin of the device. these decoup ling capacitors should receive their power from separate v dd, tv dd , bv dd , ov dd , gv dd , and lv dd and gnd power planes in the pcb, utilizing short traces to minimize inductance. capac itors may be placed directly under the device using a standard escape pattern. ot hers may surround the part. v dd av dd 2.2 f 2.2 f gnd low esl surface mount capacitors 10 2.2 f 1 0.003 f agnd_srds 1.0 av dd_srds 1. an 0805 sized capacitor is recommended for system initial bring-up. scoevdd 2.2 f 1
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 132 freescale semiconductor system design information these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , tv dd , bv dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should ha ve a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 25.4 serdes block power supply decoupling recommendations the serdes block requires a clean, tightly regulated source of power (scorevdd and xv dd ) to ensure low jitter on transmit and reliable recovery of data in the receiver. an appropria te decoupling scheme is outlined below. only surface mount technology (smt) capacitors shoul d be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. ? first, the board should have at least 10 x 10-nf smt ceramic chip capacitors as close as possible to the supply balls of the device. where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connecti ons. where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. ? second, there should be a 1-f ceramic chip capac itor on each side of the device. this should be done for all serdes supplies. ? third, between the device and any serdes voltage regulator there should be a 10-f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100-f, low esr smt tantalum chip capacitor. this shoul d be done for all serdes supplies. 25.5 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. all unused active low inputs should be tied to v dd, tv dd , bv dd , ov dd , gv dd and lv dd as required. all unused active high inputs should be conne cted to gnd. all nc (no-connect) signals must remain unconnected. power and ground connecti ons must be made to all external v dd, l vdd, tv dd , bv dd , ov dd , gv dd and gnd pins of the device. 25.6 pull-up and pull-down resistor requirements the mpc8568e requires weak pull-up resistors (2?10 k is recommended) on open drain type pins including i 2 c pins and mpic interrupt pins. correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 75 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 133 system design information refer to the pci 2.2 specification for all pull-ups required for pci. the following pins must not be pulled down during power-on reset: hreset_req, trig_out/ready/quiesce, msrcid[2:4], asleep, pa[5]. three test pins also require pull-up resistors (100 ?1 k ). these pins are l1_tstclk, l2_tstclk, and lssd_mode . these signals are for factory use only and must be pulled up to ov dd for normal machine operation. refer to the pci 2.2 specification for all pull-ups required for pci. 25.7 configuration pin muxing the mpc8568e provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins. these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. most of these sampled configuration pins are equipped with an on-chip pull-up resistors of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform /system clocks after hreset deassertion to ensure capture of the reset value). when the hreset is negated, the pull-up resistor is also disabled, thus allowing functional operation of the pin as an output with minimal signal quality or delay disrupti on. the default value for all configuration bits treated this way has been encoded such that a high vo ltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to th ese pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. the platform pll ratio and e500 pll ratio configura tion pins are not equipped with these default pull-up devices. 25.8 jtag configuration signals boundary scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all pr ocessors that implement power architecture. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signals, generally systems will assert trst during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 134 freescale semiconductor system design information to fully control the processor. if the target system ha s independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 75 allows the cop to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset so that it is asserted when the system reset signal (hreset ) is asserted. the cop header shown in figure 75 adds many benefits?breakpoints, wa tchpoints, register and memory examination/modification, and othe r standard debugger features are possible through this interface?and can be as inexpensive as an unpopulated footpr int for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). there is no standardized way to number the cop header shown in figure 75 ; consequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 75 is common to all known emulators.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 135 system design information figure 75. jtag interface connection 25.9 guidelines for high-speed interface termination 25.9.1 unused output any of the outputs that are unused should be left unconnected. these signals are: ?sd_tx[7:0] hreset hreset from target board sources hreset 13 sreset sreset nc nc 11 vdd_sense 6 5 1 15 10 10 k 10 k 10 k ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 2 notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented. connect pin 5 of the cop header to ov dd with a 10-k pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. ov dd ov dd 10 k ov dd trst 10 k ov dd 10 k 10 k chkstp_out chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pin out 1 2 nc sreset0 sreset1 3. use a nor gate with sufficient drive strength to drive two inputs. 3
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 136 freescale semiconductor ordering information ?sd_tx [7:0] 25.9.2 unused input 25.9.2.1 serdes block power not supplied if the high speed interface is not used at all, then scorevdd/xvdd/av dd_srds can be tied to gnd, all receiver inputs should be tied to the gnd as well. this includes: ?sd_rx[7:0] ?sd_rx [7:0] ?sd_ref_clk ? sd_ref_clk ? sd_rx_clk ? sd_rx_frm_ctl 25.9.2.2 serdes interface partly used if the high-speed serdes interface is partly unused, any of the unused receiver pins should be terminated as follows: ? sd_rx[7:0] = tied to scoregnd ?sd_rx [7:0] = tied to scoregnd ? sd_ref_clk = tied to scoregnd ?sd_ref_clk = tied to scoregnd note power down the unused lane through serdescr1[0:7] register (offset = 0xe_0f08) (this prevents the oscillations and holds the receiver output in a fixed state.) that maps to serdes lane 0 to lane 7 accordingly. during hreset/por, the high-speed interface must be in serial rapidio mode and/or pci express mode according to the state of the pe[8:10]. software must disable this mode through devdisr[srio] or devdisr[pcie] accordingly during software initialization. 26 ordering information contact your local freescale sales office or re gional marketing team for order information.
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 freescale semiconductor 137 ordering information 26.1 part marking parts are marked as the example shown in figure 76 . figure 76. part marking for fc-pbga device 26.2 part number decoder figure 77 shows the mpc8568e/MPC8567E number decoder. figure 77. mpc8568e part number decoder notes : mmmmm is the mask code cccc is the contry code for assembly. fc-pbga mpc856xxxxxxx is the orderable part number mpc856xxxxxxx atwlyyww mmmmm ccccc atwlyyww is the freescale assembly, year and workweek code ywwlaz ywwlaz is the trace code for assembly. mpc 856x e c vt ang j a product code device number blank: 0 - 105c c: -45(ta) - 105c qe speed ddr speed cpu speed package vt: lead free security blank: no security e: with security temperature g: 400 j: 533 an: 800 aq: 1000 au: 1333 g: 400 j: 533 die revision ppc: prototype kmpc: sample mpc: qualified 8568, 8567
mpc8568e/MPC8567E powerquicc iii integrated processor hardware specifications, rev. 1 138 freescale semiconductor document revision history 27 document revision history table 88 provides a revision history for the mpc8568e hardware specification. table 88. document revision history rev number date substantive change(s) 1 10/2010 in ta b l e 7 8 , ?mpc8568e pinout listing,? and ta b l e 7 8 , ?mpc8568e pinout listing,? added footnote 49 to lgpl4. 0 05/2009 initial public release.
document number: mpc8568eec rev. 1 10/2010 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale, the freescale logo, and powerquicc are trademarks of freescale semiconductor, inc. reg. u.s. pat. & tm. off. quicc engine is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2010 freescale semiconductor, inc.

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